1package xiangshan.frontend 2import utils._ 3import chisel3._ 4import chisel3.util._ 5import chipsalliance.rocketchip.config.Parameters 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.cache._ 9import xiangshan.cache.prefetch.L1plusPrefetcher 10import xiangshan.backend.fu.HasExceptionNO 11import system.L1CacheErrorInfo 12 13 14class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 15 16 val instrUncache = LazyModule(new InstrUncache()) 17 18 lazy val module = new FrontendImp(this) 19} 20 21 22class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 23 with HasL1plusCacheParameters 24 with HasXSParameter 25 with HasExceptionNO 26 with HasXSLog 27{ 28 val io = IO(new Bundle() { 29 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 30 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 31 val l1plusFlush = Output(Bool()) 32 val fencei = Input(Bool()) 33 val ptw = new TlbPtwIO 34 val backend = new FrontendToBackendIO 35 val sfence = Input(new SfenceBundle) 36 val tlbCsr = Input(new TlbCsrBundle) 37 val csrCtrl = Input(new CustomCSRCtrlIO) 38 val error = new L1CacheErrorInfo 39 }) 40 41 val ifu = Module(new IFU) 42 val ibuffer = Module(new Ibuffer) 43 val l1plusPrefetcher = Module(new L1plusPrefetcher) 44 val instrUncache = outer.instrUncache.module 45 46 val needFlush = io.backend.redirect_cfiUpdate.valid 47 48 // from backend 49 ifu.io.redirect <> io.backend.redirect_cfiUpdate 50 ifu.io.bp_ctrl <> io.csrCtrl.bp_ctrl 51 ifu.io.commitUpdate <> io.backend.commit_cfiUpdate 52 ifu.io.ftqEnqPtr <> io.backend.ftqEnqPtr 53 ifu.io.ftqLeftOne <> io.backend.ftqLeftOne 54 // to icache 55 val grantClientId = clientId(io.icacheMemGrant.bits.id) 56 val grantEntryId = entryId(io.icacheMemGrant.bits.id) 57 ifu.io.icacheMemGrant.valid := io.icacheMemGrant.valid && grantClientId === icacheMissQueueId.U 58 ifu.io.icacheMemGrant.bits := io.icacheMemGrant.bits 59 ifu.io.icacheMemGrant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 60 l1plusPrefetcher.io.mem_grant.valid := io.icacheMemGrant.valid && grantClientId === l1plusPrefetcherId.U 61 l1plusPrefetcher.io.mem_grant.bits := io.icacheMemGrant.bits 62 l1plusPrefetcher.io.mem_grant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 63 assert(RegNext(!l1plusPrefetcher.io.mem_grant.valid || (l1plusPrefetcher.io.mem_grant.ready && grantClientId === l1plusPrefetcherId.U))) 64 io.icacheMemGrant.ready := Mux(grantClientId === icacheMissQueueId.U, 65 ifu.io.icacheMemGrant.ready, 66 l1plusPrefetcher.io.mem_grant.ready) 67 ifu.io.fencei := io.fencei 68 69 70 instrUncache.io.req <> ifu.io.mmio_acquire 71 instrUncache.io.resp <> ifu.io.mmio_grant 72 instrUncache.io.flush <> ifu.io.mmio_flush 73 // to tlb 74 ifu.io.sfence := io.sfence 75 ifu.io.tlbCsr := io.tlbCsr 76 // from icache and l1plus prefetcher 77 io.l1plusFlush := ifu.io.l1plusFlush 78 l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid 79 l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits 80 l1plusPrefetcher.io.enable := RegNext(io.csrCtrl.l1plus_pf_enable) 81 val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients)) 82 memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq 83 memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W), 84 entryId(ifu.io.icacheMemAcq.bits.id)) 85 memAcquireArb.io.in(l1plusPrefetcherId) <> l1plusPrefetcher.io.mem_acquire 86 memAcquireArb.io.in(l1plusPrefetcherId).bits.id := Cat(l1plusPrefetcherId.U(clientIdWidth.W), 87 entryId(l1plusPrefetcher.io.mem_acquire.bits.id)) 88 io.icacheMemAcq <> memAcquireArb.io.out 89 // itlb to ptw 90 io.ptw <> ifu.io.ptw 91 // ifu to ibuffer 92 ibuffer.io.in <> ifu.io.fetchPacket 93 // backend to ibuffer 94 ibuffer.io.flush := needFlush 95 // ibuffer to backend 96 io.backend.cfVec <> ibuffer.io.out 97 // ifu to backend 98 io.backend.fetchInfo <> ifu.io.toFtq 99 100 io.error <> RegNext(ifu.io.error) 101 102 // for(out <- ibuffer.io.out){ 103 // XSInfo(out.fire(), 104 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 105 // ) 106 // } 107 108 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 109 XSPerfAccumulate("FrontendBubble", frontendBubble) 110} 111