xref: /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala (revision 45f497a4abde3fa5930268b418d634554b21b0b8) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend
18import utils._
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
23import xiangshan._
24import xiangshan.cache._
25import xiangshan.cache.mmu.{TlbRequestIO, TlbPtwIO,TLB}
26import xiangshan.backend.fu.{HasExceptionNO, PMP, PMPChecker}
27
28
29class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{
30
31  val instrUncache  = LazyModule(new InstrUncache())
32  val icache        = LazyModule(new ICache())
33
34  lazy val module = new FrontendImp(this)
35}
36
37
38class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
39  with HasXSParameter
40  with HasExceptionNO
41{
42  val io = IO(new Bundle() {
43    val fencei = Input(Bool())
44    val ptw = new TlbPtwIO(2)
45    val backend = new FrontendToCtrlIO
46    val sfence = Input(new SfenceBundle)
47    val tlbCsr = Input(new TlbCsrBundle)
48    val csrCtrl = Input(new CustomCSRCtrlIO)
49    val error  = new L1CacheErrorInfo
50    val frontendInfo = new Bundle {
51      val ibufFull  = Output(Bool())
52      val bpuInfo = new Bundle {
53        val bpRight = Output(UInt(XLEN.W))
54        val bpWrong = Output(UInt(XLEN.W))
55      }
56    }
57  })
58
59  //decouped-frontend modules
60  val bpu     = Module(new Predictor)
61  val ifu     = Module(new NewIFU)
62  val ibuffer =  Module(new Ibuffer)
63  val ftq = Module(new Ftq)
64  //icache
65
66  val tlbCsr = RegNext(io.tlbCsr)
67  // pmp
68  val pmp = Module(new PMP())
69  val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(3, sameCycle = true)).io))
70  pmp.io.distribute_csr := io.csrCtrl.distribute_csr
71  for (i <- pmp_check.indices) {
72    pmp_check(i).env.pmp  := pmp.io.pmp
73    pmp_check(i).env.mode := tlbCsr.priv.imode
74    pmp_check(i).req <> ifu.io.pmp(i).req
75    ifu.io.pmp(i).resp <> pmp_check(i).resp
76  }
77
78  io.ptw <> TLB(
79    in = Seq(ifu.io.iTLBInter(0), ifu.io.iTLBInter(1)),
80    sfence = io.sfence,
81    csr = tlbCsr,
82    width = 2,
83    shouldBlock = true,
84    itlbParams
85  )
86  //TODO: modules need to be removed
87  val instrUncache = outer.instrUncache.module
88  val icache       = outer.icache.module
89
90  icache.io.fencei := RegNext(io.fencei)
91
92  val needFlush = io.backend.toFtq.stage3Redirect.valid
93
94  //IFU-Ftq
95  ifu.io.ftqInter.fromFtq <> ftq.io.toIfu
96  ftq.io.fromIfu          <> ifu.io.ftqInter.toFtq
97  bpu.io.ftq_to_bpu       <> ftq.io.toBpu
98  ftq.io.fromBpu          <> bpu.io.bpu_to_ftq
99  //IFU-ICache
100  ifu.io.icacheInter.toIMeta    <>      icache.io.metaRead.req
101  ifu.io.icacheInter.fromIMeta  <>      icache.io.metaRead.resp
102  ifu.io.icacheInter.toIData    <>      icache.io.dataRead.req
103  ifu.io.icacheInter.fromIData  <>      icache.io.dataRead.resp
104
105  for(i <- 0 until 2){
106    ifu.io.icacheInter.toMissQueue(i)         <> icache.io.missQueue.req(i)
107    ifu.io.icacheInter.fromMissQueue(i)       <> icache.io.missQueue.resp(i)
108  }
109
110  icache.io.missQueue.flush := ifu.io.ftqInter.fromFtq.redirect.valid || (ifu.io.ftqInter.toFtq.pdWb.valid && ifu.io.ftqInter.toFtq.pdWb.bits.misOffset.valid)
111
112  //IFU-Ibuffer
113  ifu.io.toIbuffer    <> ibuffer.io.in
114
115  ftq.io.fromBackend <> io.backend.toFtq
116  io.backend.fromFtq <> ftq.io.toBackend
117  io.frontendInfo.bpuInfo <> ftq.io.bpuInfo
118
119  ibuffer.io.flush := needFlush
120  io.backend.cfVec <> ibuffer.io.out
121
122  instrUncache.io.req   <> DontCare
123  instrUncache.io.resp  <> DontCare
124  instrUncache.io.flush <> DontCare
125  io.error <> DontCare
126
127  val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid))
128  XSPerfAccumulate("FrontendBubble", frontendBubble)
129
130  io.frontendInfo.ibufFull := RegNext(ibuffer.io.full)
131}
132