xref: /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala (revision 435e467c386267af6b8ed41c5ed2741f2a2e6d05)
1package xiangshan.frontend
2import utils.XSInfo
3import chisel3._
4import chisel3.util._
5import utils.PipelineConnect
6import xiangshan._
7import xiangshan.cache._
8
9
10class Frontend extends XSModule {
11  val io = IO(new Bundle() {
12    val icacheReq = DecoupledIO(new ICacheReq)
13    val icacheResp = Flipped(DecoupledIO(new ICacheResp))
14    val icacheFlush = Output(UInt(2.W))
15    val icacheToTlb = Flipped(new BlockTlbRequestIO)
16    val ptw = new TlbPtwIO
17    val backend = new FrontendToBackendIO
18    val sfence = Input(new SfenceBundle)
19    val tlbCsr = Input(new TlbCsrBundle)
20  })
21
22  val ifu = Module(new IFU)
23  val ibuffer =  Module(new Ibuffer)
24
25  val needFlush = io.backend.redirect.valid
26
27  //backend
28  ifu.io.redirect <> io.backend.redirect
29  ifu.io.inOrderBrInfo <> io.backend.inOrderBrInfo
30  ifu.io.outOfOrderBrInfo <> io.backend.outOfOrderBrInfo
31  //icache
32  io.icacheReq <> ifu.io.icacheReq
33  io.icacheFlush <> ifu.io.icacheFlush
34  ifu.io.icacheResp <> io.icacheResp
35  //itlb to ptw
36  io.ptw <> TLB(
37    in = Seq(io.icacheToTlb),
38    sfence = io.sfence,
39    csr = io.tlbCsr,
40    width = 1,
41    isDtlb = false,
42    shouldBlock = true
43  )
44  //ibuffer
45  ibuffer.io.in <> ifu.io.fetchPacket
46  ibuffer.io.flush := needFlush
47
48  io.backend.cfVec <> ibuffer.io.out
49
50  // for(out <- ibuffer.io.out){
51  //   XSInfo(out.fire(),
52  //     p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n"
53  //   )
54  // }
55
56
57}