1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.cache._ 8 9 10class Frontend extends XSModule { 11 val io = IO(new Bundle() { 12 val backend = new FrontendToBackendIO 13 }) 14 15 val ifu = Module(new IFU) 16 val icache = ICache(enableICache = true) 17 val ibuffer = if(EnableLB) Module(new LoopBuffer) else Module(new Ibuffer) 18 19 val needFlush = io.backend.redirect.valid 20 21 //backend 22 ifu.io.redirect <> io.backend.redirect 23 ifu.io.inOrderBrInfo <> io.backend.inOrderBrInfo 24 ifu.io.outOfOrderBrInfo <> io.backend.outOfOrderBrInfo 25 26 //cache 27 icache.io.req <> ifu.io.icacheReq 28 ifu.io.icacheResp <> icache.io.resp 29 icache.io.flush := ifu.io.icacheFlush 30 31 //ibuffer 32 ibuffer.io.in <> ifu.io.fetchPacket 33 ibuffer.io.flush := needFlush 34 35 io.backend.cfVec <> ibuffer.io.out 36 37 for(out <- ibuffer.io.out){ 38 XSInfo(out.fire(), 39 p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 40 ) 41 } 42 43 44} 45