1package xiangshan.frontend 2 3import utils._ 4import chisel3._ 5import chisel3.util._ 6import chipsalliance.rocketchip.config.Parameters 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import xiangshan._ 9import xiangshan.cache._ 10import xiangshan.cache.prefetch.L1plusPrefetcher 11import xiangshan.backend.fu.HasExceptionNO 12 13class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 14 15 val instrUncache = LazyModule(new InstrUncache()) 16 17 lazy val module = new FrontendImp(this) 18} 19 20 21class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 22 with HasL1plusCacheParameters 23 with HasXSParameter 24 with HasExceptionNO 25 with HasXSLog 26{ 27 val io = IO(new Bundle() { 28 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 29 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 30 val l1plusFlush = Output(Bool()) 31 val fencei = Input(Bool()) 32 val ptw = new TlbPtwIO 33 val backend = new FrontendToBackendIO 34 val sfence = Input(new SfenceBundle) 35 val tlbCsr = Input(new TlbCsrBundle) 36 val csrCtrl = Input(new CustomCSRCtrlIO) 37 }) 38 39 val ifu = Module(new IFU) 40 val ibuffer = Module(new Ibuffer) 41 val l1plusPrefetcher = Module(new L1plusPrefetcher) 42 val instrUncache = outer.instrUncache.module 43 44 val needFlush = io.backend.redirect_cfiUpdate.valid 45 46 // from backend 47 ifu.io.redirect <> io.backend.redirect_cfiUpdate 48 ifu.io.bp_ctrl <> io.csrCtrl.bp_ctrl 49 ifu.io.commitUpdate <> io.backend.commit_cfiUpdate 50 ifu.io.ftqEnqPtr <> io.backend.ftqEnqPtr 51 ifu.io.ftqLeftOne <> io.backend.ftqLeftOne 52 // to icache 53 val grantClientId = clientId(io.icacheMemGrant.bits.id) 54 val grantEntryId = entryId(io.icacheMemGrant.bits.id) 55 ifu.io.icacheMemGrant.valid := io.icacheMemGrant.valid && grantClientId === icacheMissQueueId.U 56 ifu.io.icacheMemGrant.bits := io.icacheMemGrant.bits 57 ifu.io.icacheMemGrant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 58 l1plusPrefetcher.io.mem_grant.valid := io.icacheMemGrant.valid && grantClientId === l1plusPrefetcherId.U 59 l1plusPrefetcher.io.mem_grant.bits := io.icacheMemGrant.bits 60 l1plusPrefetcher.io.mem_grant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 61 io.icacheMemGrant.ready := Mux(grantClientId === icacheMissQueueId.U, 62 ifu.io.icacheMemGrant.ready, 63 l1plusPrefetcher.io.mem_grant.ready) 64 ifu.io.fencei := io.fencei 65 66 67 instrUncache.io.req <> ifu.io.mmio_acquire 68 instrUncache.io.resp <> ifu.io.mmio_grant 69 instrUncache.io.flush <> ifu.io.mmio_flush 70 // to tlb 71 ifu.io.sfence := io.sfence 72 ifu.io.tlbCsr := io.tlbCsr 73 // from icache and l1plus prefetcher 74 io.l1plusFlush := ifu.io.l1plusFlush 75 l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid 76 l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits 77 l1plusPrefetcher.io.enable := RegNext(io.csrCtrl.l1plus_pf_enable) 78 val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients)) 79 memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq 80 memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W), 81 entryId(ifu.io.icacheMemAcq.bits.id)) 82 memAcquireArb.io.in(l1plusPrefetcherId) <> l1plusPrefetcher.io.mem_acquire 83 memAcquireArb.io.in(l1plusPrefetcherId).bits.id := Cat(l1plusPrefetcherId.U(clientIdWidth.W), 84 entryId(l1plusPrefetcher.io.mem_acquire.bits.id)) 85 io.icacheMemAcq <> memAcquireArb.io.out 86 // itlb to ptw 87 io.ptw <> ifu.io.ptw 88 // ifu to ibuffer 89 ibuffer.io.in <> ifu.io.fetchPacket 90 // backend to ibuffer 91 ibuffer.io.flush := needFlush 92 // ibuffer to backend 93 io.backend.cfVec <> ibuffer.io.out 94 // ifu to backend 95 io.backend.fetchInfo <> ifu.io.toFtq 96 97 // for(out <- ibuffer.io.out){ 98 // XSInfo(out.fire(), 99 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 100 // ) 101 // } 102 103 104}