1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.prefetch.L1plusPrefetcher 9 10 11class Frontend extends XSModule with HasL1plusCacheParameters { 12 val io = IO(new Bundle() { 13 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 14 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 15 val l1plusFlush = Output(Bool()) 16 val fencei = Input(Bool()) 17 val ptw = new TlbPtwIO 18 val backend = new FrontendToBackendIO 19 val sfence = Input(new SfenceBundle) 20 val tlbCsr = Input(new TlbCsrBundle) 21 val mmio_acquire = DecoupledIO(new InsUncacheReq) 22 val mmio_grant = Flipped(DecoupledIO(new InsUncacheResp)) 23 val mmio_flush = Output(Bool()) 24 }) 25 26 val ifu = Module(new IFU) 27 val ibuffer = Module(new Ibuffer) 28 val l1plusPrefetcher = Module(new L1plusPrefetcher) 29 30 31 val needFlush = io.backend.redirect.valid 32 33 // from backend 34 ifu.io.redirect <> io.backend.redirect 35 ifu.io.cfiUpdateInfo <> io.backend.cfiUpdateInfo 36 // to icache 37 val grantClientId = clientId(io.icacheMemGrant.bits.id) 38 val grantEntryId = entryId(io.icacheMemGrant.bits.id) 39 ifu.io.icacheMemGrant.valid := io.icacheMemGrant.valid && grantClientId === icacheMissQueueId.U 40 ifu.io.icacheMemGrant.bits := io.icacheMemGrant.bits 41 ifu.io.icacheMemGrant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 42 io.mmio_acquire <> ifu.io.mmio_acquire 43 io.mmio_flush <> ifu.io.mmio_flush 44 ifu.io.mmio_grant <> io.mmio_grant 45 l1plusPrefetcher.io.mem_grant.valid := io.icacheMemGrant.valid && grantClientId === l1plusPrefetcherId.U 46 l1plusPrefetcher.io.mem_grant.bits := io.icacheMemGrant.bits 47 l1plusPrefetcher.io.mem_grant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 48 io.icacheMemGrant.ready := Mux(grantClientId === icacheMissQueueId.U, 49 ifu.io.icacheMemGrant.ready, 50 l1plusPrefetcher.io.mem_grant.ready) 51 ifu.io.fencei := io.fencei 52 // to tlb 53 ifu.io.sfence := io.sfence 54 ifu.io.tlbCsr := io.tlbCsr 55 // from icache and l1plus prefetcher 56 io.l1plusFlush := ifu.io.l1plusFlush 57 l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid 58 l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits 59 val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients)) 60 memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq 61 memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W), 62 entryId(ifu.io.icacheMemAcq.bits.id)) 63 memAcquireArb.io.in(l1plusPrefetcherId) <> l1plusPrefetcher.io.mem_acquire 64 memAcquireArb.io.in(l1plusPrefetcherId).bits.id := Cat(l1plusPrefetcherId.U(clientIdWidth.W), 65 entryId(l1plusPrefetcher.io.mem_acquire.bits.id)) 66 io.icacheMemAcq <> memAcquireArb.io.out 67 // itlb to ptw 68 io.ptw <> ifu.io.ptw 69 // ifu to ibuffer 70 ibuffer.io.in <> ifu.io.fetchPacket 71 // backend to ibuffer 72 ibuffer.io.flush := needFlush 73 // ibuffer to backend 74 io.backend.cfVec <> ibuffer.io.out 75 76 // for(out <- ibuffer.io.out){ 77 // XSInfo(out.fire(), 78 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 79 // ) 80 // } 81 82 83}