1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.cache._ 8 9 10class Frontend extends XSModule { 11 val io = IO(new Bundle() { 12 val icacheReq = DecoupledIO(new ICacheReq) 13 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 14 val icacheFlush = Output(UInt(2.W)) 15 val icacheToTlb = Flipped(new BlockTlbRequestIO) 16 val ptw = new TlbPtwIO 17 val backend = new FrontendToBackendIO 18 }) 19 20 val ifu = Module(new IFU) 21 val ibuffer = if(EnableLB) Module(new LoopBuffer) else Module(new Ibuffer) 22 // val ibuffer = Module(new LoopBuffer) 23 24 val needFlush = io.backend.redirect.valid 25 26 //backend 27 ifu.io.redirect <> io.backend.redirect 28 ifu.io.inOrderBrInfo <> io.backend.inOrderBrInfo 29 ifu.io.outOfOrderBrInfo <> io.backend.outOfOrderBrInfo 30 //icache 31 io.icacheReq <> ifu.io.icacheReq 32 io.icacheFlush <> ifu.io.icacheFlush 33 ifu.io.icacheResp <> io.icacheResp 34 //itlb to ptw 35 io.ptw <> TLB( 36 in = Seq(io.icacheToTlb), 37 width = 1, 38 isDtlb = false, 39 shouldBlock = true 40 ) 41 //ibuffer 42 ibuffer.io.in <> ifu.io.fetchPacket 43 ibuffer.io.flush := needFlush 44 ifu.io.loopBufPar <> ibuffer.io.loopBufPar 45 46 io.backend.cfVec <> ibuffer.io.out 47 48 49 for(out <- ibuffer.io.out){ 50 XSInfo(out.fire(), 51 p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 52 ) 53 } 54 // for(out <- ibuffer.io.out){ 55 // XSInfo(out.fire(), 56 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 57 // ) 58 // } 59 60 61} 62