109c6f1ddSLingrui98/*************************************************************************************** 209c6f1ddSLingrui98* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 309c6f1ddSLingrui98* Copyright (c) 2020-2021 Peng Cheng Laboratory 409c6f1ddSLingrui98* 509c6f1ddSLingrui98* XiangShan is licensed under Mulan PSL v2. 609c6f1ddSLingrui98* You can use this software according to the terms and conditions of the Mulan PSL v2. 709c6f1ddSLingrui98* You may obtain a copy of Mulan PSL v2 at: 809c6f1ddSLingrui98* http://license.coscl.org.cn/MulanPSL2 909c6f1ddSLingrui98* 1009c6f1ddSLingrui98* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 1109c6f1ddSLingrui98* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 1209c6f1ddSLingrui98* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 1309c6f1ddSLingrui98* 1409c6f1ddSLingrui98* See the Mulan PSL v2 for more details. 1509c6f1ddSLingrui98***************************************************************************************/ 1609c6f1ddSLingrui98 1709c6f1ddSLingrui98package xiangshan.frontend 186ab6918fSYinan Xuimport chipsalliance.rocketchip.config.Parameters 1909c6f1ddSLingrui98import chisel3._ 2009c6f1ddSLingrui98import chisel3.util._ 2109c6f1ddSLingrui98import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 226ab6918fSYinan Xuimport utils._ 233c02ee8fSwakafaimport utility._ 2409c6f1ddSLingrui98import xiangshan._ 25ee175d78SJayimport xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle} 26ee175d78SJayimport xiangshan.cache.mmu._ 271d8f4dcbSJayimport xiangshan.frontend.icache._ 2809c6f1ddSLingrui98 2909c6f1ddSLingrui98 3009c6f1ddSLingrui98class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 3109c6f1ddSLingrui98 3209c6f1ddSLingrui98 val instrUncache = LazyModule(new InstrUncache()) 3309c6f1ddSLingrui98 val icache = LazyModule(new ICache()) 3409c6f1ddSLingrui98 3509c6f1ddSLingrui98 lazy val module = new FrontendImp(this) 3609c6f1ddSLingrui98} 3709c6f1ddSLingrui98 3809c6f1ddSLingrui98 3909c6f1ddSLingrui98class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 4009c6f1ddSLingrui98 with HasXSParameter 411ca0e4f3SYinan Xu with HasPerfEvents 4209c6f1ddSLingrui98{ 4309c6f1ddSLingrui98 val io = IO(new Bundle() { 4441cb8b61SJenius val hartId = Input(UInt(8.W)) 45c4b44470SGuokai Chen val reset_vector = Input(UInt(PAddrBits.W)) 4609c6f1ddSLingrui98 val fencei = Input(Bool()) 471a718038SHaoyuan Feng val ptw = new TlbPtwIO() 4809c6f1ddSLingrui98 val backend = new FrontendToCtrlIO 4909c6f1ddSLingrui98 val sfence = Input(new SfenceBundle) 5009c6f1ddSLingrui98 val tlbCsr = Input(new TlbCsrBundle) 5109c6f1ddSLingrui98 val csrCtrl = Input(new CustomCSRCtrlIO) 52e19f7967SWilliam Wang val csrUpdate = new DistributedCSRUpdateReq 5309c6f1ddSLingrui98 val error = new L1CacheErrorInfo 5409c6f1ddSLingrui98 val frontendInfo = new Bundle { 5509c6f1ddSLingrui98 val ibufFull = Output(Bool()) 5609c6f1ddSLingrui98 val bpuInfo = new Bundle { 5709c6f1ddSLingrui98 val bpRight = Output(UInt(XLEN.W)) 5809c6f1ddSLingrui98 val bpWrong = Output(UInt(XLEN.W)) 5909c6f1ddSLingrui98 } 6009c6f1ddSLingrui98 } 6109c6f1ddSLingrui98 }) 6209c6f1ddSLingrui98 6309c6f1ddSLingrui98 //decouped-frontend modules 641d8f4dcbSJay val instrUncache = outer.instrUncache.module 651d8f4dcbSJay val icache = outer.icache.module 6609c6f1ddSLingrui98 val bpu = Module(new Predictor) 6709c6f1ddSLingrui98 val ifu = Module(new NewIFU) 6809c6f1ddSLingrui98 val ibuffer = Module(new Ibuffer) 6909c6f1ddSLingrui98 val ftq = Module(new Ftq) 7009c6f1ddSLingrui98 71f1fe8698SLemover val needFlush = RegNext(io.backend.toFtq.redirect.valid) 72d2b20d1aSTang Haojin val FlushControlRedirect = RegNext(io.backend.toFtq.redirect.bits.debugIsCtrl) 73d2b20d1aSTang Haojin val FlushMemVioRedirect = RegNext(io.backend.toFtq.redirect.bits.debugIsMemVio) 74d2b20d1aSTang Haojin val FlushControlBTBMiss = Wire(Bool()) 75d2b20d1aSTang Haojin val FlushTAGEMiss = Wire(Bool()) 76d2b20d1aSTang Haojin val FlushSCMiss = Wire(Bool()) 77d2b20d1aSTang Haojin val FlushITTAGEMiss = Wire(Bool()) 78d2b20d1aSTang Haojin val FlushRASMiss = Wire(Bool()) 79f1fe8698SLemover 806f688dacSYinan Xu val tlbCsr = DelayN(io.tlbCsr, 2) 816f688dacSYinan Xu val csrCtrl = DelayN(io.csrCtrl, 2) 82fa9f9690SLemover val sfence = RegNext(RegNext(io.sfence)) 8372951335SLi Qianruo 8472951335SLi Qianruo // trigger 856f688dacSYinan Xu ifu.io.frontendTrigger := csrCtrl.frontend_trigger 866f688dacSYinan Xu val triggerEn = csrCtrl.trigger_enable 8772951335SLi Qianruo ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 8872951335SLi Qianruo 896ee06c7aSSteve Gou // bpu ctrl 906ee06c7aSSteve Gou bpu.io.ctrl := csrCtrl.bp_ctrl 91c4b44470SGuokai Chen bpu.io.reset_vector := io.reset_vector 926ee06c7aSSteve Gou 93b6982e83SLemover// pmp 940c26d810Sguohongyu val prefetchPipeNum = ICacheParameters().prefetchPipeNum 95b6982e83SLemover val pmp = Module(new PMP()) 9634f9624dSguohongyu val pmp_check = VecInit(Seq.fill(coreParams.ipmpPortNum)(Module(new PMPChecker(3, sameCycle = true)).io)) 976f688dacSYinan Xu pmp.io.distribute_csr := csrCtrl.distribute_csr 9834f9624dSguohongyu val pmp_req_vec = Wire(Vec(coreParams.ipmpPortNum, Valid(new PMPReqBundle()))) 990c26d810Sguohongyu (0 until 2 + prefetchPipeNum).foreach(i => pmp_req_vec(i) <> icache.io.pmp(i).req) 1000c26d810Sguohongyu pmp_req_vec.last <> ifu.io.pmp.req 101ee175d78SJay 102b6982e83SLemover for (i <- pmp_check.indices) { 103ee175d78SJay pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, pmp_req_vec(i)) 104b6982e83SLemover } 1050c26d810Sguohongyu (0 until 2 + prefetchPipeNum).foreach(i => icache.io.pmp(i).resp <> pmp_check(i).resp) 1060c26d810Sguohongyu ifu.io.pmp.resp <> pmp_check.last.resp 107ee175d78SJay 10834f9624dSguohongyu val itlb = Module(new TLB(coreParams.itlbPortNum, nRespDups = 1, 1090c26d810Sguohongyu Seq(true, true) ++ Seq.fill(prefetchPipeNum)(false) ++ Seq(true), itlbParams)) 1100c26d810Sguohongyu itlb.io.requestor.take(2 + prefetchPipeNum) zip icache.io.itlb foreach {case (a,b) => a <> b} 1110c26d810Sguohongyu itlb.io.requestor.last <> ifu.io.iTLBInter // mmio may need re-tlb, blocked 1121a718038SHaoyuan Feng itlb.io.base_connect(sfence, tlbCsr) 113f1fe8698SLemover itlb.io.ptw_replenish <> DontCare 114f1fe8698SLemover itlb.io.flushPipe.map(_ := needFlush) 11509c6f1ddSLingrui98 1161a718038SHaoyuan Feng val itlb_ptw = Wire(new VectorTlbPtwIO(coreParams.itlbPortNum)) 1171a718038SHaoyuan Feng itlb_ptw.connect(itlb.io.ptw) 1181a718038SHaoyuan Feng val itlbRepeater1 = PTWFilter(itlbParams.fenceDelay, itlb_ptw, sfence, tlbCsr, l2tlbParams.ifilterSize) 1191a718038SHaoyuan Feng io.ptw <> itlbRepeater1.io.ptw 1201a718038SHaoyuan Feng 1217052722fSJay icache.io.prefetch <> ftq.io.toPrefetch 122efcb3cd3SJinYue 12309c6f1ddSLingrui98 12409c6f1ddSLingrui98 //IFU-Ftq 12509c6f1ddSLingrui98 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 126c5c5edaeSJenius ftq.io.toIfu.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 127c5c5edaeSJenius 12809c6f1ddSLingrui98 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 12909c6f1ddSLingrui98 bpu.io.ftq_to_bpu <> ftq.io.toBpu 13009c6f1ddSLingrui98 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 1311d1e6d4dSJenius 1321d1e6d4dSJenius ftq.io.mmioCommitRead <> ifu.io.mmioCommitRead 13309c6f1ddSLingrui98 //IFU-ICache 134c5c5edaeSJenius 135c5c5edaeSJenius icache.io.fetch.req <> ftq.io.toICache.req 136c5c5edaeSJenius ftq.io.toICache.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 137c5c5edaeSJenius 138c5c5edaeSJenius ifu.io.icacheInter.resp <> icache.io.fetch.resp 13950780602SJenius ifu.io.icacheInter.icacheReady := icache.io.toIFU 140d2b20d1aSTang Haojin ifu.io.icacheInter.topdownIcacheMiss := icache.io.fetch.topdownIcacheMiss 141d2b20d1aSTang Haojin ifu.io.icacheInter.topdownItlbMiss := icache.io.fetch.topdownItlbMiss 1421d8f4dcbSJay icache.io.stop := ifu.io.icacheStop 14309c6f1ddSLingrui98 1441d8f4dcbSJay ifu.io.icachePerfInfo := icache.io.perfInfo 1451d8f4dcbSJay 1466f688dacSYinan Xu icache.io.csr.distribute_csr <> csrCtrl.distribute_csr 14770899835SWilliam Wang io.csrUpdate := RegNext(icache.io.csr.update) 148e19f7967SWilliam Wang 149ecccf78fSJay icache.io.csr_pf_enable := RegNext(csrCtrl.l1I_pf_enable) 150ecccf78fSJay icache.io.csr_parity_enable := RegNext(csrCtrl.icache_parity_enable) 151ecccf78fSJay 1522a6078bfSguohongyu icache.io.fencei := io.fencei 1532a6078bfSguohongyu 15409c6f1ddSLingrui98 //IFU-Ibuffer 15509c6f1ddSLingrui98 ifu.io.toIbuffer <> ibuffer.io.in 15609c6f1ddSLingrui98 15709c6f1ddSLingrui98 ftq.io.fromBackend <> io.backend.toFtq 15809c6f1ddSLingrui98 io.backend.fromFtq <> ftq.io.toBackend 15909c6f1ddSLingrui98 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 16009c6f1ddSLingrui98 161*5359309bSGuokai Chen val checkPcMem = Reg(Vec(FtqSize, new Ftq_RF_Components)) 162*5359309bSGuokai Chen when (ftq.io.toBackend.pc_mem_wen) { 163*5359309bSGuokai Chen checkPcMem(ftq.io.toBackend.pc_mem_waddr) := ftq.io.toBackend.pc_mem_wdata 164*5359309bSGuokai Chen } 165*5359309bSGuokai Chen 166*5359309bSGuokai Chen val checkTargetIdx = Wire(Vec(DecodeWidth, UInt(log2Up(FtqSize).W))) 167*5359309bSGuokai Chen val checkTarget = Wire(Vec(DecodeWidth, UInt(VAddrBits.W))) 168*5359309bSGuokai Chen 169*5359309bSGuokai Chen for (i <- 0 until DecodeWidth) { 170*5359309bSGuokai Chen checkTargetIdx(i) := ibuffer.io.out(i).bits.ftqPtr.value 171*5359309bSGuokai Chen checkTarget(i) := Mux(ftq.io.toBackend.newest_entry_ptr.value === checkTargetIdx(i), 172*5359309bSGuokai Chen ftq.io.toBackend.newest_entry_target, 173*5359309bSGuokai Chen checkPcMem(checkTargetIdx(i) + 1.U).startAddr) 174*5359309bSGuokai Chen } 175*5359309bSGuokai Chen 176*5359309bSGuokai Chen // commented out for this br could be the last instruction in the fetch block 177*5359309bSGuokai Chen def checkNotTakenConsecutive = { 178*5359309bSGuokai Chen val prevNotTakenValid = RegInit(0.B) 179*5359309bSGuokai Chen val prevNotTakenFtqIdx = Reg(UInt(log2Up(FtqSize).W)) 180*5359309bSGuokai Chen for (i <- 0 until DecodeWidth - 1) { 181*5359309bSGuokai Chen // for instrs that is not the last, if a not-taken br, the next instr should have the same ftqPtr 182*5359309bSGuokai Chen // for instrs that is the last, record and check next request 183*5359309bSGuokai Chen when (ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr) { 184*5359309bSGuokai Chen when (ibuffer.io.out(i+1).fire) { 185*5359309bSGuokai Chen // not last br, check now 186*5359309bSGuokai Chen XSError(checkTargetIdx(i) =/= checkTargetIdx(i+1), "not-taken br should have same ftqPtr\n") 187*5359309bSGuokai Chen } .otherwise { 188*5359309bSGuokai Chen // last br, record its info 189*5359309bSGuokai Chen prevNotTakenValid := true.B 190*5359309bSGuokai Chen prevNotTakenFtqIdx := checkTargetIdx(i) 191*5359309bSGuokai Chen } 192*5359309bSGuokai Chen } 193*5359309bSGuokai Chen } 194*5359309bSGuokai Chen when (ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr) { 195*5359309bSGuokai Chen // last instr is a br, record its info 196*5359309bSGuokai Chen prevNotTakenValid := true.B 197*5359309bSGuokai Chen prevNotTakenFtqIdx := checkTargetIdx(DecodeWidth - 1) 198*5359309bSGuokai Chen } 199*5359309bSGuokai Chen when (prevNotTakenValid && ibuffer.io.out(0).fire) { 200*5359309bSGuokai Chen XSError(prevNotTakenFtqIdx =/= checkTargetIdx(0), "not-taken br should have same ftqPtr\n") 201*5359309bSGuokai Chen prevNotTakenValid := false.B 202*5359309bSGuokai Chen } 203*5359309bSGuokai Chen when (needFlush) { 204*5359309bSGuokai Chen prevNotTakenValid := false.B 205*5359309bSGuokai Chen } 206*5359309bSGuokai Chen } 207*5359309bSGuokai Chen 208*5359309bSGuokai Chen def checkTakenNotConsecutive = { 209*5359309bSGuokai Chen val prevTakenValid = RegInit(0.B) 210*5359309bSGuokai Chen val prevTakenFtqIdx = Reg(UInt(log2Up(FtqSize).W)) 211*5359309bSGuokai Chen for (i <- 0 until DecodeWidth - 1) { 212*5359309bSGuokai Chen // for instrs that is not the last, if a taken br, the next instr should not have the same ftqPtr 213*5359309bSGuokai Chen // for instrs that is the last, record and check next request 214*5359309bSGuokai Chen when (ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && ibuffer.io.out(i).bits.pred_taken) { 215*5359309bSGuokai Chen when (ibuffer.io.out(i+1).fire) { 216*5359309bSGuokai Chen // not last br, check now 217*5359309bSGuokai Chen XSError(checkTargetIdx(i) + 1.U =/= checkTargetIdx(i+1), "taken br should have consecutive ftqPtr\n") 218*5359309bSGuokai Chen } .otherwise { 219*5359309bSGuokai Chen // last br, record its info 220*5359309bSGuokai Chen prevTakenValid := true.B 221*5359309bSGuokai Chen prevTakenFtqIdx := checkTargetIdx(i) 222*5359309bSGuokai Chen } 223*5359309bSGuokai Chen } 224*5359309bSGuokai Chen } 225*5359309bSGuokai Chen when (ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr && ibuffer.io.out(DecodeWidth - 1).bits.pred_taken) { 226*5359309bSGuokai Chen // last instr is a br, record its info 227*5359309bSGuokai Chen prevTakenValid := true.B 228*5359309bSGuokai Chen prevTakenFtqIdx := checkTargetIdx(DecodeWidth - 1) 229*5359309bSGuokai Chen } 230*5359309bSGuokai Chen when (prevTakenValid && ibuffer.io.out(0).fire) { 231*5359309bSGuokai Chen XSError(prevTakenFtqIdx + 1.U =/= checkTargetIdx(0), "taken br should have consecutive ftqPtr\n") 232*5359309bSGuokai Chen prevTakenValid := false.B 233*5359309bSGuokai Chen } 234*5359309bSGuokai Chen when (needFlush) { 235*5359309bSGuokai Chen prevTakenValid := false.B 236*5359309bSGuokai Chen } 237*5359309bSGuokai Chen } 238*5359309bSGuokai Chen 239*5359309bSGuokai Chen def checkNotTakenPC = { 240*5359309bSGuokai Chen val prevNotTakenPC = Reg(UInt(VAddrBits.W)) 241*5359309bSGuokai Chen val prevIsRVC = Reg(Bool()) 242*5359309bSGuokai Chen val prevNotTakenValid = RegInit(0.B) 243*5359309bSGuokai Chen 244*5359309bSGuokai Chen for (i <- 0 until DecodeWidth - 1) { 245*5359309bSGuokai Chen when (ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && !ibuffer.io.out(i).bits.pred_taken) { 246*5359309bSGuokai Chen when (ibuffer.io.out(i+1).fire) { 247*5359309bSGuokai Chen XSError(ibuffer.io.out(i).bits.pc + Mux(ibuffer.io.out(i).bits.pd.isRVC, 2.U, 4.U) =/= ibuffer.io.out(i+1).bits.pc, "not-taken br should have consecutive pc\n") 248*5359309bSGuokai Chen } .otherwise { 249*5359309bSGuokai Chen prevNotTakenValid := true.B 250*5359309bSGuokai Chen prevIsRVC := ibuffer.io.out(i).bits.pd.isRVC 251*5359309bSGuokai Chen prevNotTakenPC := ibuffer.io.out(i).bits.pc 252*5359309bSGuokai Chen } 253*5359309bSGuokai Chen } 254*5359309bSGuokai Chen } 255*5359309bSGuokai Chen when (ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr && !ibuffer.io.out(DecodeWidth - 1).bits.pred_taken) { 256*5359309bSGuokai Chen prevNotTakenValid := true.B 257*5359309bSGuokai Chen prevIsRVC := ibuffer.io.out(DecodeWidth - 1).bits.pd.isRVC 258*5359309bSGuokai Chen prevNotTakenPC := ibuffer.io.out(DecodeWidth - 1).bits.pc 259*5359309bSGuokai Chen } 260*5359309bSGuokai Chen when (prevNotTakenValid && ibuffer.io.out(0).fire) { 261*5359309bSGuokai Chen XSError(prevNotTakenPC + Mux(prevIsRVC, 2.U, 4.U) =/= ibuffer.io.out(0).bits.pc, "not-taken br should have same pc\n") 262*5359309bSGuokai Chen prevNotTakenValid := false.B 263*5359309bSGuokai Chen } 264*5359309bSGuokai Chen when (needFlush) { 265*5359309bSGuokai Chen prevNotTakenValid := false.B 266*5359309bSGuokai Chen } 267*5359309bSGuokai Chen } 268*5359309bSGuokai Chen 269*5359309bSGuokai Chen def checkTakenPC = { 270*5359309bSGuokai Chen val prevTakenFtqIdx = Reg(UInt(log2Up(FtqSize).W)) 271*5359309bSGuokai Chen val prevTakenValid = RegInit(0.B) 272*5359309bSGuokai Chen val prevTakenTarget = Wire(UInt(VAddrBits.W)) 273*5359309bSGuokai Chen prevTakenTarget := checkPcMem(prevTakenFtqIdx + 1.U).startAddr 274*5359309bSGuokai Chen 275*5359309bSGuokai Chen for (i <- 0 until DecodeWidth - 1) { 276*5359309bSGuokai Chen when (ibuffer.io.out(i).fire && !ibuffer.io.out(i).bits.pd.notCFI && ibuffer.io.out(i).bits.pred_taken) { 277*5359309bSGuokai Chen when (ibuffer.io.out(i+1).fire) { 278*5359309bSGuokai Chen XSError(checkTarget(i) =/= ibuffer.io.out(i+1).bits.pc, "taken instr should follow target pc\n") 279*5359309bSGuokai Chen } .otherwise { 280*5359309bSGuokai Chen prevTakenValid := true.B 281*5359309bSGuokai Chen prevTakenFtqIdx := checkTargetIdx(i) 282*5359309bSGuokai Chen } 283*5359309bSGuokai Chen } 284*5359309bSGuokai Chen } 285*5359309bSGuokai Chen when (ibuffer.io.out(DecodeWidth - 1).fire && !ibuffer.io.out(DecodeWidth - 1).bits.pd.notCFI && ibuffer.io.out(DecodeWidth - 1).bits.pred_taken) { 286*5359309bSGuokai Chen prevTakenValid := true.B 287*5359309bSGuokai Chen prevTakenFtqIdx := checkTargetIdx(DecodeWidth - 1) 288*5359309bSGuokai Chen } 289*5359309bSGuokai Chen when (prevTakenValid && ibuffer.io.out(0).fire) { 290*5359309bSGuokai Chen XSError(prevTakenTarget =/= ibuffer.io.out(0).bits.pc, "taken instr should follow target pc\n") 291*5359309bSGuokai Chen prevTakenValid := false.B 292*5359309bSGuokai Chen } 293*5359309bSGuokai Chen when (needFlush) { 294*5359309bSGuokai Chen prevTakenValid := false.B 295*5359309bSGuokai Chen } 296*5359309bSGuokai Chen } 297*5359309bSGuokai Chen 298*5359309bSGuokai Chen //checkNotTakenConsecutive 299*5359309bSGuokai Chen checkTakenNotConsecutive 300*5359309bSGuokai Chen checkTakenPC 301*5359309bSGuokai Chen checkNotTakenPC 302*5359309bSGuokai Chen 303a37fbf10SJay ifu.io.rob_commits <> io.backend.toFtq.rob_commits 304a37fbf10SJay 30509c6f1ddSLingrui98 ibuffer.io.flush := needFlush 306d2b20d1aSTang Haojin ibuffer.io.ControlRedirect := FlushControlRedirect 307d2b20d1aSTang Haojin ibuffer.io.MemVioRedirect := FlushMemVioRedirect 308d2b20d1aSTang Haojin ibuffer.io.ControlBTBMissBubble := FlushControlBTBMiss 309d2b20d1aSTang Haojin ibuffer.io.TAGEMissBubble := FlushTAGEMiss 310d2b20d1aSTang Haojin ibuffer.io.SCMissBubble := FlushSCMiss 311d2b20d1aSTang Haojin ibuffer.io.ITTAGEMissBubble := FlushITTAGEMiss 312d2b20d1aSTang Haojin ibuffer.io.RASMissBubble := FlushRASMiss 313d2b20d1aSTang Haojin 314d2b20d1aSTang Haojin FlushControlBTBMiss := ftq.io.ControlBTBMissBubble 315d2b20d1aSTang Haojin FlushTAGEMiss := ftq.io.TAGEMissBubble 316d2b20d1aSTang Haojin FlushSCMiss := ftq.io.SCMissBubble 317d2b20d1aSTang Haojin FlushITTAGEMiss := ftq.io.ITTAGEMissBubble 318d2b20d1aSTang Haojin FlushRASMiss := ftq.io.RASMissBubble 319d2b20d1aSTang Haojin 32009c6f1ddSLingrui98 io.backend.cfVec <> ibuffer.io.out 321d2b20d1aSTang Haojin io.backend.stallReason <> ibuffer.io.stallReason 322d2b20d1aSTang Haojin dontTouch(io.backend.stallReason) 32309c6f1ddSLingrui98 3240be662e4SJay instrUncache.io.req <> ifu.io.uncacheInter.toUncache 3250be662e4SJay ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 32658dbdfc2SJay instrUncache.io.flush := false.B 32758dbdfc2SJay io.error <> RegNext(RegNext(icache.io.error)) 32809c6f1ddSLingrui98 32941cb8b61SJenius icache.io.hartId := io.hartId 33041cb8b61SJenius 33109c6f1ddSLingrui98 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 33209c6f1ddSLingrui98 XSPerfAccumulate("FrontendBubble", frontendBubble) 33309c6f1ddSLingrui98 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 334cd365d4cSrvcoresjw 3351ca0e4f3SYinan Xu // PFEvent 3361ca0e4f3SYinan Xu val pfevent = Module(new PFEvent) 3371ca0e4f3SYinan Xu pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 3381ca0e4f3SYinan Xu val csrevents = pfevent.io.hpmevent.take(8) 339cd365d4cSrvcoresjw 3401ca0e4f3SYinan Xu val allPerfEvents = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerf) 3411ca0e4f3SYinan Xu override val perfEvents = HPerfMonitor(csrevents, allPerfEvents).getPerfEvents 3421ca0e4f3SYinan Xu generatePerfEvent() 34309c6f1ddSLingrui98} 344