1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import chisel3.experimental.chiselName 25 26trait BimParams extends HasXSParameter { 27 val bimSize = 2048 28 val bypassEntries = 4 29} 30 31@chiselName 32class BIM(implicit p: Parameters) extends BasePredictor with BimParams with BPUUtils { 33 val bimAddr = new TableAddr(log2Up(bimSize), 1) 34 35 val bim = Module(new SRAMTemplate(UInt(2.W), set = bimSize, way=numBr, shouldReset = false, holdRead = true)) 36 37 val doing_reset = RegInit(true.B) 38 val resetRow = RegInit(0.U(log2Ceil(bimSize).W)) 39 resetRow := resetRow + doing_reset 40 when (resetRow === (bimSize-1).U) { doing_reset := false.B } 41 42 val s0_idx = bimAddr.getIdx(s0_pc) 43 44 bim.io.r.req.valid := io.s0_fire 45 bim.io.r.req.bits.setIdx := s0_idx 46 47 io.in.ready := bim.io.r.req.ready 48 io.s1_ready := bim.io.r.req.ready 49 50 val s1_read = bim.io.r.resp.data 51 52 io.out.resp := io.in.bits.resp_in(0) 53 54 val s1_latch_taken_mask = VecInit(Cat((0 until numBr reverse).map(i => s1_read(i)(1))).asBools()) 55 val s1_latch_meta = s1_read.asUInt() 56 override val meta_size = s1_latch_meta.getWidth 57 58 io.out.resp.s1.preds.taken_mask := s1_latch_taken_mask 59 io.out.resp.s2.preds.taken_mask := RegEnable(s1_latch_taken_mask, 0.U.asTypeOf(Vec(numBr, Bool())), io.s1_fire) 60 61 io.out.resp.s3.preds.taken_mask := RegEnable(RegEnable(s1_latch_taken_mask, io.s1_fire), io.s2_fire) 62 io.out.s3_meta := RegEnable(RegEnable(s1_latch_meta, io.s1_fire), io.s2_fire) 63 64 // Update logic 65 val u_valid = RegNext(io.update.valid) 66 val update = RegNext(io.update.bits) 67 68 val u_idx = bimAddr.getIdx(update.pc) 69 70 // Bypass logic 71 val wrbypass_ctrs = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(numBr, UInt(2.W))))) 72 val wrbypass_ctr_valids = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(numBr, Bool())))) 73 val wrbypass_idx = RegInit(0.U.asTypeOf(Vec(bypassEntries, UInt(log2Up(bimSize).W)))) 74 val wrbypass_enq_ptr = RegInit(0.U(log2Up(bypassEntries).W)) 75 76 val wrbypass_hits = VecInit((0 until bypassEntries).map(i => 77 !doing_reset && wrbypass_idx(i) === u_idx)) 78 val wrbypass_hit = wrbypass_hits.reduce(_||_) 79 val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) 80 81 val oldCtrs = VecInit((0 until numBr).map(i => 82 Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(i), 83 wrbypass_ctrs(wrbypass_hit_idx)(i), update.meta(2*i+1, 2*i)))) 84 85 val newTakens = update.preds.taken_mask 86 val newCtrs = VecInit((0 until numBr).map(i => 87 satUpdate(oldCtrs(i), 2, newTakens(i)) 88 )) 89 90 val update_mask = LowerMask(PriorityEncoderOH(update.preds.taken_mask.asUInt)) 91 val need_to_update = VecInit((0 until numBr).map(i => u_valid && update.ftb_entry.brValids(i) && update_mask(i))) 92 93 when (reset.asBool) { wrbypass_ctr_valids.foreach(_ := VecInit(Seq.fill(numBr)(false.B)))} 94 95 for (i <- 0 until numBr) { 96 when(need_to_update.reduce(_||_)) { 97 when(wrbypass_hit) { 98 when(need_to_update(i)) { 99 wrbypass_ctrs(wrbypass_hit_idx)(i) := newCtrs(i) 100 wrbypass_ctr_valids(wrbypass_hit_idx)(i) := true.B 101 } 102 }.otherwise { 103 wrbypass_ctr_valids(wrbypass_enq_ptr)(i) := false.B 104 when(need_to_update(i)) { 105 wrbypass_ctrs(wrbypass_enq_ptr)(i) := newCtrs(i) 106 wrbypass_ctr_valids(wrbypass_enq_ptr)(i) := true.B 107 } 108 } 109 } 110 } 111 112 when (need_to_update.reduce(_||_) && !wrbypass_hit) { 113 wrbypass_idx(wrbypass_enq_ptr) := u_idx 114 wrbypass_enq_ptr := (wrbypass_enq_ptr + 1.U)(log2Up(bypassEntries)-1, 0) 115 } 116 117 bim.io.w.apply( 118 valid = need_to_update.asUInt.orR || doing_reset, 119 data = Mux(doing_reset, VecInit(Seq.fill(numBr)(2.U(2.W))), newCtrs), 120 setIdx = Mux(doing_reset, resetRow, u_idx), 121 waymask = Mux(doing_reset, Fill(numBr, 1.U(1.W)).asUInt(), need_to_update.asUInt()) 122 ) 123 124 val latch_s0_fire = RegNext(io.s0_fire) 125 126 XSDebug(doing_reset, "Doing reset...\n") 127 128 XSDebug(io.s0_fire, "req_pc=%x, req_idx=%d\n", s0_pc, s0_idx) 129 130 for(i <- 0 until numBr) { 131 XSDebug(latch_s0_fire, "last_cycle req %d: ctr=%b\n", i.U, s1_read(i)) 132 } 133 134 XSDebug(u_valid, "update_pc=%x, update_idx=%d, is_br=%b\n", update.pc, u_idx, update.ftb_entry.brValids.asUInt) 135 136 XSDebug(u_valid, "newTakens=%b\n", newTakens.asUInt) 137 138 for(i <- 0 until numBr) { 139 XSDebug(u_valid, "oldCtrs%d=%b\n", i.U, oldCtrs(i)) 140 } 141 142 for(i <- 0 until numBr) { 143 XSDebug(u_valid, "newCtrs%d=%b\n", i.U, newCtrs(i)) 144 } 145 146} 147