xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision 5c5bd416ce761d956348a8e2fbbf268922371d8b) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import chisel3.experimental.chiselName
8
9trait BimParams extends HasXSParameter {
10  val BimBanks = PredictWidth
11  val BimSize = 4096
12  val nRows = BimSize / BimBanks
13  val bypassEntries = 4
14}
15
16@chiselName
17class BIM extends BasePredictor with BimParams {
18  class BIMResp extends Resp {
19    val ctrs = Vec(PredictWidth, UInt(2.W))
20  }
21  class BIMMeta extends Meta {
22    val ctrs = Vec(PredictWidth, UInt(2.W))
23  }
24  class BIMFromOthers extends FromOthers {}
25
26  class BIMIO extends DefaultBasePredictorIO {
27    val resp = Output(new BIMResp)
28    val meta = Output(new BIMMeta)
29  }
30
31  override val io = IO(new BIMIO)
32  override val debug = true
33
34  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
35
36  val bim = Module(new SRAMTemplate(UInt(2.W), set = nRows, way=BimBanks, shouldReset = false, holdRead = true))
37
38  val doing_reset = RegInit(true.B)
39  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
40  resetRow := resetRow + doing_reset
41  when (resetRow === (nRows-1).U) { doing_reset := false.B }
42
43  val if1_packetAlignedPC = packetAligned(io.pc.bits)
44  val if2_pc = RegEnable(if1_packetAlignedPC, io.pc.valid)
45
46  val if1_mask = io.inMask
47  val if1_row  = bimAddr.getBankIdx(if1_packetAlignedPC)
48
49  bim.io.r.req.valid := io.pc.valid
50  bim.io.r.req.bits.setIdx := if1_row
51
52  val if2_bimRead = bim.io.r.resp.data
53  val ctrlMask = Fill(if2_bimRead.getWidth, ctrl.bim_enable.asUInt).asTypeOf(if2_bimRead)
54  io.resp.ctrs  := VecInit(if2_bimRead zip ctrlMask map {case (a, b) => a & b})
55  io.meta.ctrs  := if2_bimRead
56
57  val updateValid = RegNext(io.update.valid)
58  val u = RegNext(io.update.bits)
59
60  val updateRow = bimAddr.getBankIdx(u.ftqPC)
61
62
63  val wrbypass_ctrs       = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, UInt(2.W)))))
64  val wrbypass_ctr_valids = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, Bool()))))
65  val wrbypass_rows     = RegInit(0.U.asTypeOf(Vec(bypassEntries, UInt(log2Up(nRows).W))))
66  val wrbypass_enq_idx  = RegInit(0.U(log2Up(bypassEntries).W))
67
68  val wrbypass_hits = VecInit((0 until bypassEntries).map( i =>
69    !doing_reset && wrbypass_rows(i) === updateRow))
70  val wrbypass_hit = wrbypass_hits.reduce(_||_)
71  val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
72
73  val oldCtrs = VecInit((0 until BimBanks).map(b =>
74                  Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(b),
75                    wrbypass_ctrs(wrbypass_hit_idx)(b), u.metas(b).bimCtr)))
76
77  val newTakens = VecInit((0 until BimBanks).map(b => u.cfiIndex.valid && u.cfiIndex.bits === b.U))
78  val newCtrs = VecInit((0 until BimBanks).map(b => satUpdate(oldCtrs(b), 2, newTakens(b))))
79  // val oldSaturated = newCtr === oldCtr
80
81  val needToUpdate = VecInit((0 until PredictWidth).map(i => updateValid && u.br_mask(i) && u.valids(i)))
82
83  when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
84
85  for (b <- 0 until BimBanks) {
86    when (needToUpdate.reduce(_||_)) {
87      when (wrbypass_hit) {
88        when (needToUpdate(b)) {
89          wrbypass_ctrs(wrbypass_hit_idx)(b) := newCtrs(b)
90          wrbypass_ctr_valids(wrbypass_hit_idx)(b) := true.B
91        }
92      }.otherwise {
93        wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B
94        when (needToUpdate(b)) {
95          wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B
96          wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b)
97        }
98      }
99    }
100  }
101
102  when (needToUpdate.reduce(_||_) && !wrbypass_hit) {
103    wrbypass_rows(wrbypass_enq_idx) := updateRow
104    wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
105  }
106
107  bim.io.w.apply(
108    valid = needToUpdate.asUInt.orR || doing_reset,
109    data = Mux(doing_reset, VecInit(Seq.fill(BimBanks)(2.U(2.W))), newCtrs),
110    setIdx = Mux(doing_reset, resetRow, updateRow),
111    waymask = Mux(doing_reset, Fill(BimBanks, "b1".U).asUInt, needToUpdate.asUInt)
112  )
113
114  XSPerfAccumulate("bim_wrbypass_hit", needToUpdate.reduce(_||_) && wrbypass_hit)
115  XSPerfAccumulate("bim_wrbypass_enq", needToUpdate.reduce(_||_) && !wrbypass_hit)
116
117  if (BPUDebug && debug) {
118    val u = io.update.bits
119    XSDebug(doing_reset, "Reseting...\n")
120    XSDebug("[update] v=%d pc=%x valids=%b, tgt=%x\n", updateValid, u.ftqPC, u.valids.asUInt, u.target)
121
122    XSDebug("[update] brMask=%b, taken=%b isMisPred=%b\n", u.br_mask.asUInt, newTakens.asUInt, u.mispred.asUInt)
123    for (i <- 0 until BimBanks) {
124      XSDebug(RegNext(io.pc.valid && io.inMask(i)), p"BimResp[$i]: ctr = ${io.resp.ctrs(i)}\n")
125      XSDebug(needToUpdate(i),
126        p"update bim bank $i: pc:${Hexadecimal(u.ftqPC)}, taken:${u.takens(i)}, " +
127        p"oldCtr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n")
128      XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(i) && needToUpdate(i),
129        p"bank $i wrbypass hit wridx $wrbypass_hit_idx: row:$updateRow, " +
130        p"ctr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n")
131      XSDebug(true.B, p"bimCtr(${i.U})=${Binary(u.metas(i).bimCtr)} oldCtr=${Binary(oldCtrs(i))} newCtr=${Binary(newCtrs(i))}\n")
132    }
133  }
134
135}
136