1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest._ 23import freechips.rocketchip.util.SRAMAnnotation 24import xiangshan._ 25import utils._ 26import utility._ 27import xiangshan.backend.fu.{PMPChecker, PMPReqBundle, PMPConfig => XSPMPConfig} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.backend.fu.util.HasCSRConst 30import freechips.rocketchip.rocket.PMPConfig 31 32/** TLB module 33 * support block request and non-block request io at the same time 34 * return paddr at next cycle, then go for pmp/pma check 35 * @param Width: The number of requestors 36 * @param Block: Blocked or not for each requestor ports 37 * @param q: TLB Parameters, like entry number, each TLB has its own parameters 38 * @param p: XiangShan Paramemters, like XLEN 39 */ 40 41class TLB(Width: Int, nRespDups: Int = 1, Block: Seq[Boolean], q: TLBParameters)(implicit p: Parameters) extends TlbModule 42 with HasCSRConst 43 with HasPerfEvents 44{ 45 val io = IO(new TlbIO(Width, nRespDups, q)) 46 47 val req = io.requestor.map(_.req) 48 val resp = io.requestor.map(_.resp) 49 val ptw = io.ptw 50 val pmp = io.pmp 51 val refill_to_mem = io.refill_to_mem 52 53 /** Sfence.vma & Svinval 54 * Sfence.vma will 1. flush old entries 2. flush inflight 3. flush pipe 55 * Svinval will 1. flush old entries 2. flush inflight 56 * So, Svinval will not flush pipe, which means 57 * it should not drop reqs from pipe and should return right resp 58 */ 59 val sfence = DelayN(io.sfence, q.fenceDelay) 60 val csr = io.csr 61 val satp = DelayN(io.csr.satp, q.fenceDelay) 62 val vsatp = DelayN(io.csr.vsatp, q.fenceDelay) 63 val hgatp = DelayN(io.csr.hgatp, q.fenceDelay) 64 65 val flush_mmu = DelayN(sfence.valid || csr.satp.changed || csr.vsatp.changed || csr.hgatp.changed, q.fenceDelay) 66 val mmu_flush_pipe = DelayN(sfence.valid && sfence.bits.flushPipe, q.fenceDelay) // for svinval, won't flush pipe 67 val flush_pipe = io.flushPipe 68 69 val isHyperInst = (0 until Width).map(i => ValidHold(req(i).fire && !req(i).bits.kill && req(i).bits.hyperinst, resp(i).fire, flush_pipe(i))) 70 val onlyS2xlate = vsatp.mode === 0.U && hgatp.mode === 8.U 71 72 // ATTENTION: csr and flush from backend are delayed. csr should not be later than flush. 73 // because, csr will influence tlb behavior. 74 val ifecth = if (q.fetchi) true.B else false.B 75 val mode_tmp = if (q.useDmode) csr.priv.dmode else csr.priv.imode 76 val mode = (0 until Width).map(i => Mux(isHyperInst(i), csr.priv.spvp, mode_tmp)) 77 val virt = csr.priv.virt 78 val sum = (0 until Width).map(i => Mux(virt || isHyperInst(i), io.csr.priv.vsum, io.csr.priv.sum)) 79 val mxr = (0 until Width).map(i => Mux(virt || isHyperInst(i), io.csr.priv.vmxr || io.csr.priv.mxr, io.csr.priv.mxr)) 80 81 // val vmEnable = satp.mode === 8.U // && (mode < ModeM) // FIXME: fix me when boot xv6/linux... 82 val vmEnable = (0 until Width).map(i => if (EnbaleTlbDebug) (satp.mode === 8.U) 83 else (satp.mode === 8.U) && (mode(i) < ModeM)) 84 val s2xlateEnable = (0 until Width).map(i => (isHyperInst(i) || virt) && (vsatp.mode === 8.U || hgatp.mode === 8.U) && (mode(i) < ModeM)) 85 val portTranslateEnable = (0 until Width).map(i => (vmEnable(i) || s2xlateEnable(i)) && RegNext(!req(i).bits.no_translate)) 86 87 val req_in = req 88 val req_out = req.map(a => RegEnable(a.bits, a.fire)) 89 val req_out_v = (0 until Width).map(i => ValidHold(req_in(i).fire && !req_in(i).bits.kill, resp(i).fire, flush_pipe(i))) 90 91 val refill = (0 until Width).map(i => ptw.resp.fire && !flush_mmu && (vmEnable(i) || ptw.resp.bits.s2xlate =/= noS2xlate)) 92 refill_to_mem := DontCare 93 val entries = Module(new TlbStorageWrapper(Width, q, nRespDups)) 94 entries.io.base_connect(sfence, csr, satp) 95 if (q.outReplace) { io.replace <> entries.io.replace } 96 for (i <- 0 until Width) { 97 val s2xlate = Wire(UInt(2.W)) 98 s2xlate := MuxCase(noS2xlate, Seq( 99 (!(virt || req_in(i).bits.hyperinst)) -> noS2xlate, 100 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 101 (vsatp.mode === 0.U) -> onlyStage2, 102 (hgatp.mode === 0.U) -> onlyStage1 103 )) 104 entries.io.r_req_apply(io.requestor(i).req.valid, get_pn(req_in(i).bits.vaddr), i, s2xlate) 105 entries.io.w_apply(refill(i), ptw.resp.bits) 106 resp(i).bits.debug.isFirstIssue := RegNext(req(i).bits.debug.isFirstIssue) 107 resp(i).bits.debug.robIdx := RegNext(req(i).bits.debug.robIdx) 108 } 109 val need_gpa = RegInit(false.B) 110 val need_gpa_vpn = Reg(UInt(vpnLen.W)) 111 val need_gpa_gvpn = Reg(UInt(vpnLen.W)) 112 val hasGpf = Wire(Vec(Width, Bool())) 113 // read TLB, get hit/miss, paddr, perm bits 114 val readResult = (0 until Width).map(TLBRead(_)) 115 val hitVec = readResult.map(_._1) 116 val missVec = readResult.map(_._2) 117 val pmp_addr = readResult.map(_._3) 118 val perm = readResult.map(_._4) 119 val g_perm = readResult.map(_._7) 120 val s2xlate = readResult.map(_._8) 121 // check pmp use paddr (for timing optization, use pmp_addr here) 122 // check permisson 123 (0 until Width).foreach{i => 124 pmp_check(pmp_addr(i), req_out(i).size, req_out(i).cmd, i) 125 for (d <- 0 until nRespDups) { 126 perm_check(perm(i)(d), req_out(i).cmd, i, d, g_perm(i)(d), req_out(i).hlvx, s2xlate(i)) 127 } 128 hasGpf(i) := resp(i).bits.excp(0).gpf.ld || resp(i).bits.excp(0).gpf.st || resp(i).bits.excp(0).gpf.instr 129 } 130 131 // handle block or non-block io 132 // for non-block io, just return the above result, send miss to ptw 133 // for block io, hold the request, send miss to ptw, 134 // when ptw back, return the result 135 (0 until Width) foreach {i => 136 if (Block(i)) handle_block(i) 137 else handle_nonblock(i) 138 } 139 io.ptw.resp.ready := true.B 140 141 /************************ main body above | method/log/perf below ****************************/ 142 def TLBRead(i: Int) = { 143 val s2xlate = Wire(UInt(2.W)) 144 s2xlate := MuxCase(noS2xlate, Seq( 145 (!(virt || req_in(i).bits.hyperinst)) -> noS2xlate, 146 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 147 (vsatp.mode === 0.U) -> onlyStage2, 148 (hgatp.mode === 0.U) -> onlyStage1 149 )) 150 val (e_hit, e_ppn, e_perm, e_super_hit, e_super_ppn, static_pm, e_g_perm, e_s2xlate) = entries.io.r_resp_apply(i) 151 val (p_hit, p_ppn, p_perm, p_gvpn, p_g_perm, p_s2xlate) = ptw_resp_bypass(get_pn(req_in(i).bits.vaddr), s2xlate) 152 val enable = portTranslateEnable(i) 153 154 val need_gpa_vpn_hit = RegNext(need_gpa_vpn === get_pn(req_in(i).bits.vaddr)) 155 when (ptw.resp.fire && need_gpa_vpn === ptw.resp.bits.getVpn) { 156 need_gpa_gvpn := p_gvpn 157 } 158 when (hasGpf(i) && need_gpa === false.B) { 159 need_gpa := true.B 160 need_gpa_vpn := get_pn(req_in(i).bits.vaddr) 161 } 162 when (e_hit && need_gpa && need_gpa_vpn === get_pn(req_in(i).bits.vaddr)){ 163 need_gpa := false.B 164 } 165 166 val hit = e_hit || p_hit 167 val miss = (!hit && enable) || !(hasGpf(i) && need_gpa_vpn_hit) 168 hit.suggestName(s"hit_read_${i}") 169 miss.suggestName(s"miss_read_${i}") 170 171 val vaddr = SignExt(req_out(i).vaddr, PAddrBits) 172 resp(i).bits.miss := miss 173 resp(i).bits.ptwBack := ptw.resp.fire 174 resp(i).bits.memidx := RegNext(req_in(i).bits.memidx) 175 176 val ppn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(ppnLen.W)))) 177 val perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 178 val gvpn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(vpnLen.W)))) 179 val g_perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 180 val r_s2xlate = WireInit(VecInit(Seq.fill(nRespDups)(0.U(2.W)))) 181 for (d <- 0 until nRespDups) { 182 ppn(d) := Mux(p_hit, p_ppn, e_ppn(d)) 183 perm(d) := Mux(p_hit, p_perm, e_perm(d)) 184 gvpn(d) := need_gpa_gvpn 185 g_perm(d) := Mux(p_hit, p_g_perm, e_g_perm(d)) 186 r_s2xlate(d) := Mux(p_hit, p_s2xlate, e_s2xlate(d)) 187 val paddr = Cat(ppn(d), get_off(req_out(i).vaddr)) 188 val gpaddr = Cat(gvpn(d), get_off(req_out(i).vaddr)) 189 resp(i).bits.paddr(d) := Mux(enable, paddr, vaddr) 190 resp(i).bits.gpaddr(d) := Mux(r_s2xlate(d) === onlyStage2, vaddr, gpaddr) 191 } 192 193 XSDebug(req_out_v(i), p"(${i.U}) hit:${hit} miss:${miss} ppn:${Hexadecimal(ppn(0))} perm:${perm(0)}\n") 194 195 val pmp_paddr = resp(i).bits.paddr(0) 196 197 (hit, miss, pmp_paddr, perm, g_perm, s2xlate) 198 } 199 200 def pmp_check(addr: UInt, size: UInt, cmd: UInt, idx: Int): Unit = { 201 pmp(idx).valid := resp(idx).valid 202 pmp(idx).bits.addr := addr 203 pmp(idx).bits.size := size 204 pmp(idx).bits.cmd := cmd 205 } 206 207 def perm_check(perm: TlbPermBundle, cmd: UInt, idx: Int, nDups: Int, g_perm: TlbPermBundle, hlvx: Bool, s2xlate: UInt) = { 208 // for timing optimization, pmp check is divided into dynamic and static 209 // dynamic: superpage (or full-connected reg entries) -> check pmp when translation done 210 // static: 4K pages (or sram entries) -> check pmp with pre-checked results 211 val hasS2xlate = s2xlate =/= noS2xlate 212 val onlyS2 = s2xlate === onlyS2xlate 213 val af = perm.af || (hasS2xlate && g_perm.af) 214 215 // Stage 1 perm check 216 val pf = perm.pf || (hlvx && !perm.x) 217 val ldUpdate = !perm.a && TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd) // update A/D through exception 218 val stUpdate = (!perm.a || !perm.d) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) // update A/D through exception 219 val instrUpdate = !perm.a && TlbCmd.isExec(cmd) // update A/D through exception 220 val modeCheck = !(mode(idx) === ModeU && !perm.u || mode(idx) === ModeS && perm.u && (!sum(idx) || ifecth)) 221 val ldPermFail = !(modeCheck && (perm.r || mxr(idx) && perm.x)) 222 val stPermFail = !(modeCheck && perm.w) 223 val instrPermFail = !(modeCheck && perm.x) 224 val ldPf = (ldPermFail || pf) && (TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd)) 225 val stPf = (stPermFail || pf) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 226 val instrPf = (instrPermFail || pf) && TlbCmd.isExec(cmd) 227 val s1_valid = portTranslateEnable(idx) && !onlyS2 228 229 // Stage 2 perm check 230 val gpf = g_perm.pf || (hlvx && !g_perm.x) 231 val g_ldUpdate = !g_perm.a && TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd) 232 val g_stUpdate = (!g_perm.a || !g_perm.d) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 233 val g_instrUpdate = !g_perm.a && TlbCmd.isExec(cmd) 234 val g_ldPermFail = !(g_perm.r || io.csr.priv.mxr && g_perm.x) 235 val g_stPermFail = !g_perm.w 236 val g_instrPermFail = !g_perm.x 237 val ldGpf = (g_ldPermFail || gpf) && (TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd)) 238 val stGpf = (g_stPermFail || gpf) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 239 val instrGpf = (g_instrPermFail || gpf) && TlbCmd.isExec(cmd) 240 val s2_valid = hasS2xlate 241 242 val fault_valid = s1_valid || s2_valid 243 244 resp(idx).bits.excp(nDups).pf.ld := (ldPf || ldUpdate) && s1_valid && !af 245 resp(idx).bits.excp(nDups).pf.st := (stPf || stUpdate) && s1_valid && !af 246 resp(idx).bits.excp(nDups).pf.instr := (instrPf || instrUpdate) && s1_valid && !af 247 // NOTE: pf need && with !af, page fault has higher priority than access fault 248 // but ptw may also have access fault, then af happens, the translation is wrong. 249 // In this case, pf has lower priority than af 250 251 resp(idx).bits.excp(nDups).gpf.ld := (ldGpf || g_ldUpdate) && s2_valid && !af 252 resp(idx).bits.excp(nDups).gpf.st := (stGpf || g_stUpdate) && s2_valid && !af 253 resp(idx).bits.excp(nDups).gpf.instr := (instrGpf || g_instrUpdate) && s2_valid && !af 254 255 resp(idx).bits.excp(nDups).af.ld := af && TlbCmd.isRead(cmd) && fault_valid 256 resp(idx).bits.excp(nDups).af.st := af && TlbCmd.isWrite(cmd) && fault_valid 257 resp(idx).bits.excp(nDups).af.instr := af && TlbCmd.isExec(cmd) && fault_valid 258 259 260 } 261 262 def handle_nonblock(idx: Int): Unit = { 263 io.requestor(idx).resp.valid := req_out_v(idx) 264 io.requestor(idx).req.ready := io.requestor(idx).resp.ready // should always be true 265 XSError(!io.requestor(idx).resp.ready, s"${q.name} port ${idx} is non-block, resp.ready must be true.B") 266 267 val req_need_gpa = hasGpf(idx) 268 val req_s2xlate = Wire(UInt(2.W)) 269 req_s2xlate := MuxCase(noS2xlate, Seq( 270 (!(virt || req_in(idx).bits.hyperinst)) -> noS2xlate, 271 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 272 (vsatp.mode === 0.U) -> onlyStage2, 273 (hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 274 )) 275 val ptw_s2xlate = ptw.resp.bits.s2xlate =/= noS2xlate 276 val onlyS2 = ptw_s2xlate === onlyStage2 277 val ptw_s1_hit = ptw.resp.bits.s1.hit(get_pn(req_out(idx).vaddr), Mux(ptw_s2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.asid, true, false, ptw_s2xlate) 278 val ptw_s2_hit = ptw.resp.bits.s2.hit(get_pn(req_out(idx).vaddr), io.csr.hgatp.asid) 279 val ptw_just_back = ptw.resp.fire && req_s2xlate === ptw_s2xlate && Mux(onlyS2, ptw_s2_hit, ptw_s1_hit) 280 val ptw_already_back = RegNext(ptw.resp.fire) && RegNext(ptw.resp.bits).hit(get_pn(req_out(idx).vaddr), asid = io.csr.satp.asid, allType = true) 281 io.ptw.req(idx).valid := req_out_v(idx) && (missVec(idx)) && !(ptw_just_back || ptw_already_back) // TODO: remove the regnext, timing 282 io.tlbreplay(idx) := req_out_v(idx) && missVec(idx) && (ptw_just_back || ptw_already_back) 283 when (io.requestor(idx).req_kill && RegNext(io.requestor(idx).req.fire)) { 284 io.ptw.req(idx).valid := false.B 285 io.tlbreplay(idx) := true.B 286 } 287 io.ptw.req(idx).bits.vpn := get_pn(req_out(idx).vaddr) 288 io.ptw.req(idx).bits.s2xlate := RegNext(req_s2xlate) 289 io.ptw.req(idx).bits.memidx := req_out(idx).memidx 290 } 291 292 def handle_block(idx: Int): Unit = { 293 // three valid: 1.if exist a entry; 2.if sent to ptw; 3.unset resp.valid 294 io.requestor(idx).req.ready := !req_out_v(idx) || io.requestor(idx).resp.fire 295 // req_out_v for if there is a request, may long latency, fixme 296 297 // miss request entries 298 val req_need_gpa = hasGpf(idx) 299 val miss_req_vpn = get_pn(req_out(idx).vaddr) 300 val miss_req_memidx = req_out(idx).memidx 301 val miss_req_s2xlate = Wire(UInt(2.W)) 302 miss_req_s2xlate := MuxCase(noS2xlate, Seq( 303 (!(virt || req_in(idx).bits.hyperinst)) -> noS2xlate, 304 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 305 (vsatp.mode === 0.U) -> onlyStage2, 306 (hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 307 )) 308 val miss_req_s2xlate_reg = RegEnable(miss_req_s2xlate, io.ptw.req(idx).fire()) 309 val hasS2xlate = miss_req_s2xlate_reg =/= noS2xlate 310 val onlyS2 = miss_req_s2xlate_reg === onlyStage2 311 val hit_s1 = io.ptw.resp.bits.s1.hit(miss_req_vpn, Mux(hasS2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.asid, allType = true, false, hasS2xlate) 312 val hit_s2 = io.ptw.resp.bits.s2.hit(miss_req_vpn, io.csr.hgatp.asid) 313 val hit = Mux(onlyS2, hit_s2, hit_s1) && io.ptw.resp.valid && miss_req_s2xlate_reg === io.ptw.resp.bits.s2xlate 314 315 val new_coming = RegNext(req_in(idx).fire && !req_in(idx).bits.kill && !flush_pipe(idx), false.B) 316 val miss_wire = new_coming && missVec(idx) 317 val miss_v = ValidHoldBypass(miss_wire, resp(idx).fire, flush_pipe(idx)) 318 val miss_req_v = ValidHoldBypass(miss_wire || (miss_v && flush_mmu && !mmu_flush_pipe), 319 io.ptw.req(idx).fire || resp(idx).fire, flush_pipe(idx)) 320 321 // when ptw resp, check if hit, reset miss_v, resp to lsu/ifu 322 resp(idx).valid := req_out_v(idx) && !(miss_v && portTranslateEnable(idx)) 323 when (io.ptw.resp.fire && hit && req_out_v(idx) && portTranslateEnable(idx)) { 324 val stage1 = io.ptw.resp.bits.s1 325 val stage2 = io.ptw.resp.bits.s2 326 val s2xlate = io.ptw.resp.bits.s2xlate 327 resp(idx).valid := true.B 328 resp(idx).bits.miss := false.B 329 val s1_paddr = Cat(stage1.genPPN(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr)) 330 val s2_paddr = Cat(stage2.genPPNS2(), get_off(req_out(idx).vaddr)) 331 for (d <- 0 until nRespDups) { 332 resp(idx).bits.paddr(d) := Mux(s2xlate =/= noS2xlate, s2_paddr, s1_paddr) 333 resp(idx).bits.gpaddr(d) := s1_paddr 334 perm_check(stage1, req_out(idx).cmd, idx, d, stage2, req_out(idx).hlvx, s2xlate) 335 } 336 pmp_check(resp(idx).bits.paddr(0), req_out(idx).size, req_out(idx).cmd, idx) 337 338 // NOTE: the unfiltered req would be handled by Repeater 339 } 340 assert(RegNext(!resp(idx).valid || resp(idx).ready, true.B), "when tlb resp valid, ready should be true, must") 341 assert(RegNext(req_out_v(idx) || !(miss_v || miss_req_v), true.B), "when not req_out_v, should not set miss_v/miss_req_v") 342 343 val ptw_req = io.ptw.req(idx) 344 ptw_req.valid := miss_req_v 345 ptw_req.bits.vpn := miss_req_vpn 346 ptw_req.bits.s2xlate := miss_req_s2xlate 347 ptw_req.bits.memidx := miss_req_memidx 348 349 io.tlbreplay(idx) := false.B 350 351 // NOTE: when flush pipe, tlb should abandon last req 352 // however, some outside modules like icache, dont care flushPipe, and still waiting for tlb resp 353 // just resp valid and raise page fault to go through. The pipe(ifu) will abandon it. 354 if (!q.outsideRecvFlush) { 355 when (req_out_v(idx) && flush_pipe(idx) && portTranslateEnable(idx)) { 356 resp(idx).valid := true.B 357 for (d <- 0 until nRespDups) { 358 resp(idx).bits.excp(d).pf.ld := true.B // sfence happened, pf for not to use this addr 359 resp(idx).bits.excp(d).pf.st := true.B 360 resp(idx).bits.excp(d).pf.instr := true.B 361 } 362 } 363 } 364 } 365 366 // when ptw resp, tlb at refill_idx maybe set to miss by force. 367 // Bypass ptw resp to check. 368 def ptw_resp_bypass(vpn: UInt, s2xlate: UInt) = { 369 val hasS2xlate = s2xlate =/= noS2xlate 370 val onlyS2 = s2xlate === onlyStage2 371 val onlyS1 = s2xlate === onlyStage1 372 val s2xlate_hit = s2xlate === ptw.resp.bits.s2xlate 373 val normal_hit = ptw.resp.bits.s1.hit(vpn, Mux(hasS2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.asid, true, false, hasS2xlate) 374 val onlyS2_hit = ptw.resp.bits.s2.hit(vpn, io.csr.hgatp.asid) 375 val p_hit = RegNext(Mux(onlyS2, onlyS2_hit, normal_hit) && io.ptw.resp.fire && s2xlate_hit) 376 val ppn_s1 = ptw.resp.bits.s1.genPPN(vpn) 377 val ppn_s2 = ptw.resp.bits.s2.genPPNS2() 378 val p_ppn = RegEnable(Mux(hasS2xlate, ppn_s2, ppn_s1), io.ptw.resp.fire) 379 val p_perm = RegEnable(ptwresp_to_tlbperm(ptw.resp.bits.s1), io.ptw.resp.fire) 380 val p_gvpn = RegEnable(Mux(onlyS1, Cat(ptw.resp.bits.s1.entry.tag, ptw.resp.bits.s1.ppn_low(OHToUInt(ptw.resp.bits.s1.pteidx))), ptw.resp.bits.s2.entry.tag), io.ptw.resp.fire) 381 val p_g_perm = RegEnable(hptwresp_to_tlbperm(ptw.resp.bits.s2), io.ptw.resp.fire) 382 val p_s2xlate = RegEnable(ptw.resp.bits.s2xlate, io.ptw.resp.fire) 383 (p_hit, p_ppn, p_perm, p_gvpn, p_g_perm, p_s2xlate) 384 } 385 386 // assert 387 for(i <- 0 until Width) { 388 TimeOutAssert(req_out_v(i) && !resp(i).valid, timeOutThreshold, s"{q.name} port{i} long time no resp valid.") 389 } 390 391 // perf event 392 val result_ok = req_in.map(a => RegNext(a.fire)) 393 val perfEvents = 394 Seq( 395 ("access", PopCount((0 until Width).map{i => if (Block(i)) io.requestor(i).req.fire else portTranslateEnable(i) && result_ok(i) })), 396 ("miss ", PopCount((0 until Width).map{i => if (Block(i)) portTranslateEnable(i) && result_ok(i) && missVec(i) else ptw.req(i).fire })), 397 ) 398 generatePerfEvent() 399 400 // perf log 401 for (i <- 0 until Width) { 402 if (Block(i)) { 403 XSPerfAccumulate(s"access${i}",result_ok(i) && portTranslateEnable(i)) 404 XSPerfAccumulate(s"miss${i}", result_ok(i) && missVec(i)) 405 } else { 406 XSPerfAccumulate("first_access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && RegNext(req(i).bits.debug.isFirstIssue)) 407 XSPerfAccumulate("access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i)) 408 XSPerfAccumulate("first_miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i) && RegNext(req(i).bits.debug.isFirstIssue)) 409 XSPerfAccumulate("miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i)) 410 } 411 } 412 XSPerfAccumulate("ptw_resp_count", ptw.resp.fire) 413 XSPerfAccumulate("ptw_resp_pf_count", ptw.resp.fire && ptw.resp.bits.s1.pf) 414 415 // Log 416 for(i <- 0 until Width) { 417 XSDebug(req(i).valid, p"req(${i.U}): (${req(i).valid} ${req(i).ready}) ${req(i).bits}\n") 418 XSDebug(resp(i).valid, p"resp(${i.U}): (${resp(i).valid} ${resp(i).ready}) ${resp(i).bits}\n") 419 } 420 421 XSDebug(io.sfence.valid, p"Sfence: ${io.sfence}\n") 422 XSDebug(ParallelOR(req_out_v) || ptw.resp.valid, p"vmEnable:${vmEnable} hit:${Binary(VecInit(hitVec).asUInt)} miss:${Binary(VecInit(missVec).asUInt)}\n") 423 for (i <- ptw.req.indices) { 424 XSDebug(ptw.req(i).fire, p"L2TLB req:${ptw.req(i).bits}\n") 425 } 426 XSDebug(ptw.resp.valid, p"L2TLB resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n") 427 428 println(s"${q.name}: page: ${q.NWays} ${q.Associative} ${q.Replacer.get}") 429 430 if (env.EnableDifftest) { 431 for (i <- 0 until Width) { 432 val pf = io.requestor(i).resp.bits.excp(0).pf.instr || io.requestor(i).resp.bits.excp(0).pf.st || io.requestor(i).resp.bits.excp(0).pf.ld 433 val gpf = io.requestor(i).resp.bits.excp(0).gpf.instr || io.requestor(i).resp.bits.excp(0).gpf.st || io.requestor(i).resp.bits.excp(0).gpf.ld 434 val af = io.requestor(i).resp.bits.excp(0).af.instr || io.requestor(i).resp.bits.excp(0).af.st || io.requestor(i).resp.bits.excp(0).af.ld 435 val difftest = DifftestModule(new DiffL1TLBEvent) 436 difftest.coreid := io.hartId 437 difftest.valid := RegNext(io.requestor(i).req.fire) && !io.requestor(i).req_kill && io.requestor(i).resp.fire && !io.requestor(i).resp.bits.miss && !pf && !af && !gpf && portTranslateEnable(i) 438 if (!Seq("itlb", "ldtlb", "sttlb").contains(q.name)) { 439 difftest.valid := false.B 440 } 441 difftest.index := TLBDiffId(p(XSCoreParamsKey).HartId).U 442 difftest.satp := io.csr.satp 443 difftest.vpn := RegNext(get_pn(req_in(i).bits.vaddr)) 444 difftest.ppn := get_pn(io.requestor(i).resp.bits.paddr(0)) 445 difftest.satp := Cat(io.csr.satp.mode, io.csr.satp.asid, io.csr.satp.ppn) 446 difftest.vsatp := Cat(io.csr.vsatp.mode, io.csr.vsatp.asid, io.csr.vsatp.ppn) 447 difftest.hgatp := Cat(io.csr.hgatp.mode, io.csr.hgatp.asid, io.csr.hgatp.ppn) 448 val s2xlate = Wire(UInt(2.W)) 449 s2xlate := MuxCase(noS2xlate, Seq( 450 (!(virt || req_in(i).bits.hyperinst)) -> noS2xlate, 451 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 452 (vsatp.mode === 0.U) -> onlyStage2, 453 (hgatp.mode === 0.U) -> onlyStage1 454 )) 455 difftest.s2xlate := s2xlate 456 } 457 } 458} 459 460object TLBDiffId { 461 var i: Int = 0 462 var lastHartId: Int = -1 463 def apply(hartId: Int): Int = { 464 if (lastHartId != hartId) { 465 i = 0 466 lastHartId = hartId 467 } 468 i += 1 469 i - 1 470 } 471} 472 473class TLBNonBlock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(false), q) 474class TLBBLock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(true), q) 475 476class TlbReplace(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule { 477 val io = IO(new TlbReplaceIO(Width, q)) 478 479 if (q.Associative == "fa") { 480 val re = ReplacementPolicy.fromString(q.Replacer, q.NWays) 481 re.access(io.page.access.map(_.touch_ways)) 482 io.page.refillIdx := re.way 483 } else { // set-acco && plru 484 val re = ReplacementPolicy.fromString(q.Replacer, q.NSets, q.NWays) 485 re.access(io.page.access.map(_.sets), io.page.access.map(_.touch_ways)) 486 io.page.refillIdx := { if (q.NWays == 1) 0.U else re.way(io.page.chosen_set) } 487 } 488} 489