1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* Copyright (c) 2024-2025 Institute of Information Engineering, Chinese Academy of Sciences 6* 7* XiangShan is licensed under Mulan PSL v2. 8* You can use this software according to the terms and conditions of the Mulan PSL v2. 9* You may obtain a copy of Mulan PSL v2 at: 10* http://license.coscl.org.cn/MulanPSL2 11* 12* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 13* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 14* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 15* 16* See the Mulan PSL v2 for more details. 17***************************************************************************************/ 18 19package xiangshan.cache.mmu 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import utility._ 28import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 29import freechips.rocketchip.tilelink._ 30import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 31 32/** Page Table Walk is divided into two parts 33 * One, PTW: page walk for pde, except for leaf entries, one by one 34 * Two, LLPTW: page walk for pte, only the leaf entries(4KB), in parallel 35 */ 36 37 38/** PTW : page table walker 39 * a finite state machine 40 * only take 1GB and 2MB page walks 41 * or in other words, except the last level(leaf) 42 **/ 43class PTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 44 val req = Flipped(DecoupledIO(new Bundle { 45 val req_info = new L2TlbInnerBundle() 46 val l3Hit = if (EnableSv48) Some(new Bool()) else None 47 val l2Hit = Bool() 48 val ppn = UInt(ptePPNLen.W) 49 val stage1Hit = Bool() 50 val stage1 = new PtwMergeResp 51 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 52 val jmp_bitmap_check = Bool() // super page in PtwCache ptw hit, but need bitmap check 53 val pte = UInt(XLEN.W) // Page Table Entry 54 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 55 val SPlevel = UInt(log2Up(Level).W) 56 }) 57 })) 58 val resp = DecoupledIO(new Bundle { 59 val source = UInt(bSourceWidth.W) 60 val s2xlate = UInt(2.W) 61 val resp = new PtwMergeResp 62 val h_resp = new HptwResp 63 }) 64 65 val llptw = DecoupledIO(new LLPTWInBundle()) 66 // NOTE: llptw change from "connect to llptw" to "connect to page cache" 67 // to avoid corner case that caused duplicate entries 68 69 val hptw = new Bundle { 70 val req = DecoupledIO(new Bundle { 71 val source = UInt(bSourceWidth.W) 72 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 73 val gvpn = UInt(ptePPNLen.W) 74 }) 75 val resp = Flipped(Valid(new Bundle { 76 val h_resp = Output(new HptwResp) 77 })) 78 } 79 val mem = new Bundle { 80 val req = DecoupledIO(new L2TlbMemReqBundle()) 81 val resp = Flipped(ValidIO(UInt(XLEN.W))) 82 val mask = Input(Bool()) 83 } 84 val pmp = new Bundle { 85 val req = ValidIO(new PMPReqBundle()) 86 val resp = Flipped(new PMPRespBundle()) 87 } 88 89 val refill = Output(new Bundle { 90 val req_info = new L2TlbInnerBundle() 91 val level = UInt(log2Up(Level + 1).W) 92 }) 93 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 94 val req = DecoupledIO(new bitmapReqBundle()) 95 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 96 }) 97} 98 99class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 100 val io = IO(new PTWIO) 101 val sfence = io.sfence 102 val mem = io.mem 103 val req_s2xlate = Reg(UInt(2.W)) 104 val enableS2xlate = req_s2xlate =/= noS2xlate 105 val onlyS1xlate = req_s2xlate === onlyStage1 106 val onlyS2xlate = req_s2xlate === onlyStage2 107 108 // mbmc:bitmap csr 109 val mbmc = io.csr.mbmc 110 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 111 112 val satp = Wire(new TlbSatpBundle()) 113 when (io.req.fire) { 114 satp := Mux(io.req.bits.req_info.s2xlate =/= noS2xlate, io.csr.vsatp, io.csr.satp) 115 } .otherwise { 116 satp := Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 117 } 118 val s1Pbmte = Mux(req_s2xlate =/= noS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 119 120 val mode = satp.mode 121 val hgatp = io.csr.hgatp 122 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 123 val s2xlate = enableS2xlate && !onlyS1xlate 124 val level = RegInit(3.U(log2Up(Level + 1).W)) 125 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 126 val gpf_level = RegInit(3.U(log2Up(Level + 1).W)) 127 val ppn = Reg(UInt(ptePPNLen.W)) 128 val vpn = Reg(UInt(vpnLen.W)) // vpn or gvpn(onlyS2xlate) 129 val levelNext = level - 1.U 130 val l3Hit = Reg(Bool()) 131 val l2Hit = Reg(Bool()) 132 val jmp_bitmap_check_w = if (HasBitmapCheck) { io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.bits.req_info.s2xlate =/= onlyStage2 } else { false.B } 133 val jmp_bitmap_check_r = if (HasBitmapCheck) { RegEnable(jmp_bitmap_check_w, io.req.fire) } else { false.B } 134 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.fire)) 135 val pte = if (HasBitmapCheck) { Mux(jmp_bitmap_check_r, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) } else { mem.resp.bits.asTypeOf(new PteBundle()) } 136 137 // s/w register 138 val s_pmp_check = RegInit(true.B) 139 val s_mem_req = RegInit(true.B) 140 val s_llptw_req = RegInit(true.B) 141 val w_mem_resp = RegInit(true.B) 142 val s_hptw_req = RegInit(true.B) 143 val w_hptw_resp = RegInit(true.B) 144 val s_last_hptw_req = RegInit(true.B) 145 val w_last_hptw_resp = RegInit(true.B) 146 // for updating "level" 147 val mem_addr_update = RegInit(false.B) 148 149 val s_bitmap_check = RegInit(true.B) 150 val w_bitmap_resp = RegInit(true.B) 151 val whether_need_bitmap_check = RegInit(false.B) 152 val bitmap_checkfailed = RegInit(false.B) 153 154 val idle = RegInit(true.B) 155 val finish = WireInit(false.B) 156 val vs_finish = WireInit(false.B) // need to wait for G-stage translate, should not do pmp check 157 158 val hptw_pageFault = RegInit(false.B) 159 val hptw_accessFault = RegInit(false.B) 160 val need_last_s2xlate = RegInit(false.B) 161 val stage1Hit = RegEnable(io.req.bits.stage1Hit, io.req.fire) 162 val stage1 = RegEnable(io.req.bits.stage1, io.req.fire) 163 val hptw_resp_stage2 = Reg(Bool()) 164 val first_gvpn_check_fail = RegInit(false.B) 165 166 // use accessfault repersent bitmap check failed 167 val pte_isAf = Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 168 val ppn_af = if (HasBitmapCheck) { 169 Mux(enableS2xlate, Mux(onlyS1xlate, pte_isAf, false.B), pte_isAf) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 170 } else { 171 Mux(enableS2xlate, Mux(onlyS1xlate, pte.isAf(), false.B), pte.isAf()) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 172 } 173 val pte_valid = RegInit(false.B) // avoid l1tlb pf from stage1 when gpf happens in the first s2xlate in PTW 174 175 val pageFault = pte.isPf(level, s1Pbmte) 176 val find_pte = pte.isLeaf() || ppn_af || pageFault 177 val to_find_pte = level === 1.U && find_pte === false.B 178 val source = RegEnable(io.req.bits.req_info.source, io.req.fire) 179 180 val sent_to_pmp = idle === false.B && (s_pmp_check === false.B || mem_addr_update) && !finish && !vs_finish && !first_gvpn_check_fail && !(find_pte && pte_valid) 181 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, false.B, sent_to_pmp) 182 183 val l3addr = Wire(UInt(ptePaddrLen.W)) 184 val l2addr = Wire(UInt(ptePaddrLen.W)) 185 val l1addr = Wire(UInt(ptePaddrLen.W)) 186 val hptw_addr = Wire(UInt(ptePaddrLen.W)) 187 val mem_addr = Wire(UInt(PAddrBits.W)) 188 189 l3addr := MakeAddr(satp.ppn, getVpnn(vpn, 3)) 190 if (EnableSv48) { 191 when (mode === Sv48) { 192 l2addr := MakeAddr(Mux(l3Hit, ppn, pte.getPPN()), getVpnn(vpn, 2)) 193 } .otherwise { 194 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 195 } 196 } else { 197 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 198 } 199 l1addr := MakeAddr(Mux(l2Hit, ppn, pte.getPPN()), getVpnn(vpn, 1)) 200 hptw_addr := Mux(af_level === 3.U, l3addr, Mux(af_level === 2.U, l2addr, l1addr)) 201 mem_addr := hptw_addr(PAddrBits - 1, 0) 202 203 val hptw_resp = Reg(new HptwResp) 204 205 val update_full_gvpn_mem_resp = RegInit(false.B) 206 val full_gvpn_reg = Reg(UInt(ptePPNLen.W)) 207 val full_gvpn_wire = pte.getPPN() 208 val full_gvpn = Mux(update_full_gvpn_mem_resp, full_gvpn_wire, full_gvpn_reg) 209 210 val gpaddr = MuxCase(hptw_addr, Seq( 211 (stage1Hit || onlyS2xlate) -> Cat(full_gvpn, 0.U(offLen.W)), 212 !s_last_hptw_req -> Cat(MuxLookup(level, pte.getPPN())(Seq( 213 3.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 3), vpn(vpnnLen * 3 - 1, 0)), 214 2.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 2), vpn(vpnnLen * 2 - 1, 0)), 215 1.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen), vpn(vpnnLen - 1, 0) 216 ))), 217 0.U(offLen.W)) 218 )) 219 val gvpn_gpf = 220 (!(hptw_pageFault || hptw_accessFault || ((pageFault || ppn_af) && pte_valid)) && 221 Mux( 222 s2xlate && io.csr.hgatp.mode === Sv39x4, 223 full_gvpn(ptePPNLen - 1, GPAddrBitsSv39x4 - offLen) =/= 0.U, 224 Mux( 225 s2xlate && io.csr.hgatp.mode === Sv48x4, 226 full_gvpn(ptePPNLen - 1, GPAddrBitsSv48x4 - offLen) =/= 0.U, 227 false.B 228 ) 229 )) || first_gvpn_check_fail 230 231 val guestFault = hptw_pageFault || hptw_accessFault || gvpn_gpf 232 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 233 val fake_h_resp = WireInit(0.U.asTypeOf(new HptwResp)) 234 fake_h_resp.entry.tag := get_pn(gpaddr) 235 fake_h_resp.entry.vmid.map(_ := io.csr.hgatp.vmid) 236 fake_h_resp.gpf := true.B 237 238 val fake_pte = WireInit(0.U.asTypeOf(new PteBundle())) 239 fake_pte.perm.v := false.B // tell L1TLB this is fake pte 240 fake_pte.ppn := ppn(ppnLen - 1, 0) 241 fake_pte.ppn_high := ppn(ptePPNLen - 1, ppnLen) 242 243 io.req.ready := idle 244 val ptw_resp = Wire(new PtwMergeResp) 245 ptw_resp.apply(Mux(pte_valid, pageFault && !accessFault, false.B), accessFault || (ppn_af && !(pte_valid && (pageFault || guestFault))), Mux(accessFault, af_level, Mux(guestFault, gpf_level, level)), Mux(pte_valid, pte, fake_pte), vpn, satp.asid, hgatp.vmid, vpn(sectortlbwidth - 1, 0), not_super = false, not_merge = false, bitmap_checkfailed.asBool) 246 247 val normal_resp = idle === false.B && mem_addr_update && !need_last_s2xlate && (guestFault || (w_mem_resp && find_pte) || (s_pmp_check && accessFault) || onlyS2xlate ) 248 val stageHit_resp = idle === false.B && hptw_resp_stage2 249 io.resp.valid := Mux(stage1Hit, stageHit_resp, normal_resp) 250 io.resp.bits.source := source 251 io.resp.bits.resp := Mux(stage1Hit || (l3Hit || l2Hit) && guestFault && !pte_valid, stage1, ptw_resp) 252 io.resp.bits.h_resp := Mux(gvpn_gpf, fake_h_resp, hptw_resp) 253 io.resp.bits.s2xlate := req_s2xlate 254 255 io.llptw.valid := s_llptw_req === false.B && to_find_pte && !accessFault && !guestFault 256 io.llptw.bits.req_info.source := source 257 io.llptw.bits.req_info.vpn := vpn 258 io.llptw.bits.req_info.s2xlate := req_s2xlate 259 io.llptw.bits.ppn := DontCare 260 if (HasBitmapCheck) { 261 io.llptw.bits.bitmapCheck.get.jmp_bitmap_check := DontCare 262 io.llptw.bits.bitmapCheck.get.ptes := DontCare 263 io.llptw.bits.bitmapCheck.get.cfs := DontCare 264 io.llptw.bits.bitmapCheck.get.hitway := DontCare 265 } 266 267 io.pmp.req.valid := DontCare // samecycle, do not use valid 268 io.pmp.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 269 io.pmp.req.bits.size := 3.U // TODO: fix it 270 io.pmp.req.bits.cmd := TlbCmd.read 271 272 if (HasBitmapCheck) { 273 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 274 io.bitmap.get.req.valid := !s_bitmap_check 275 io.bitmap.get.req.bits.bmppn := pte.ppn 276 io.bitmap.get.req.bits.id := FsmReqID.U(bMemID.W) 277 io.bitmap.get.req.bits.vpn := vpn 278 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check_r, cache_level, level) 279 io.bitmap.get.req.bits.way_info := DontCare 280 io.bitmap.get.req.bits.hptw_bypassed := false.B 281 io.bitmap.get.resp.ready := !w_bitmap_resp 282 } 283 mem.req.valid := s_mem_req === false.B && !mem.mask && !accessFault && s_pmp_check 284 mem.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 285 mem.req.bits.id := FsmReqID.U(bMemID.W) 286 mem.req.bits.hptw_bypassed := false.B 287 288 io.refill.req_info.s2xlate := req_s2xlate 289 io.refill.req_info.vpn := vpn 290 io.refill.level := level 291 io.refill.req_info.source := source 292 293 io.hptw.req.valid := !s_hptw_req || !s_last_hptw_req 294 io.hptw.req.bits.id := FsmReqID.U(bMemID.W) 295 io.hptw.req.bits.gvpn := get_pn(gpaddr) 296 io.hptw.req.bits.source := source 297 298 if (HasBitmapCheck) { 299 when (io.req.fire && jmp_bitmap_check_w) { 300 idle := false.B 301 req_s2xlate := io.req.bits.req_info.s2xlate 302 vpn := io.req.bits.req_info.vpn 303 s_bitmap_check := false.B 304 need_last_s2xlate := false.B 305 hptw_pageFault := false.B 306 hptw_accessFault := false.B 307 level := io.req.bits.bitmapCheck.get.SPlevel 308 pte_valid := true.B 309 accessFault := false.B 310 } 311 } 312 313 when (io.req.fire && io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 314 idle := false.B 315 req_s2xlate := io.req.bits.req_info.s2xlate 316 s_last_hptw_req := false.B 317 hptw_resp_stage2 := false.B 318 need_last_s2xlate := false.B 319 hptw_pageFault := false.B 320 hptw_accessFault := false.B 321 full_gvpn_reg := io.req.bits.stage1.genPPN() 322 } 323 324 when (io.resp.fire && stage1Hit){ 325 idle := true.B 326 } 327 328 when (io.req.fire && !io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 329 val req = io.req.bits 330 val gvpn_wire = Wire(UInt(ptePPNLen.W)) 331 if (EnableSv48) { 332 when (mode === Sv48) { 333 level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 334 af_level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 335 gpf_level := Mux(req.l2Hit, 2.U, Mux(req.l3Hit.get, 3.U, 0.U)) 336 ppn := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 337 l3Hit := req.l3Hit.get 338 gvpn_wire := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 339 } .otherwise { 340 level := Mux(req.l2Hit, 1.U, 2.U) 341 af_level := Mux(req.l2Hit, 1.U, 2.U) 342 gpf_level := Mux(req.l2Hit, 2.U, 0.U) 343 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 344 l3Hit := false.B 345 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 346 } 347 } else { 348 level := Mux(req.l2Hit, 1.U, 2.U) 349 af_level := Mux(req.l2Hit, 1.U, 2.U) 350 gpf_level := Mux(req.l2Hit, 2.U, 0.U) 351 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 352 l3Hit := false.B 353 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 354 } 355 vpn := io.req.bits.req_info.vpn 356 l2Hit := req.l2Hit 357 accessFault := false.B 358 idle := false.B 359 hptw_pageFault := false.B 360 hptw_accessFault := false.B 361 pte_valid := false.B 362 req_s2xlate := io.req.bits.req_info.s2xlate 363 when(io.req.bits.req_info.s2xlate === onlyStage2){ 364 full_gvpn_reg := io.req.bits.req_info.vpn 365 val onlys2_gpaddr = Cat(io.req.bits.req_info.vpn, 0.U(offLen.W)) // is 50 bits, don't need to check high bits when sv48x4 is enabled 366 val check_gpa_high_fail = Mux(io.req.bits.req_info.s2xlate === onlyStage2 && io.csr.hgatp.mode === Sv39x4, onlys2_gpaddr(onlys2_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, false.B) 367 need_last_s2xlate := false.B 368 when(check_gpa_high_fail){ 369 mem_addr_update := true.B 370 first_gvpn_check_fail := true.B 371 }.otherwise{ 372 s_last_hptw_req := false.B 373 } 374 }.elsewhen(io.req.bits.req_info.s2xlate === allStage){ 375 full_gvpn_reg := 0.U 376 val allstage_gpaddr = Cat(gvpn_wire, 0.U(offLen.W)) 377 val check_gpa_high_fail = Mux(io.csr.hgatp.mode === Sv39x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, Mux(io.csr.hgatp.mode === Sv48x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv48x4) =/= 0.U, false.B)) 378 when(check_gpa_high_fail){ 379 mem_addr_update := true.B 380 first_gvpn_check_fail := true.B 381 }.otherwise{ 382 need_last_s2xlate := true.B 383 s_hptw_req := false.B 384 } 385 }.otherwise { 386 full_gvpn_reg := 0.U 387 need_last_s2xlate := false.B 388 s_pmp_check := false.B 389 } 390 } 391 392 when(io.hptw.req.fire && s_hptw_req === false.B){ 393 s_hptw_req := true.B 394 w_hptw_resp := false.B 395 } 396 397 when(io.hptw.resp.fire && w_hptw_resp === false.B) { 398 w_hptw_resp := true.B 399 val g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 400 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 401 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 402 hptw_resp := io.hptw.resp.bits.h_resp 403 hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 404 when(!(g_perm_fail || io.hptw.resp.bits.h_resp.gpf || io.hptw.resp.bits.h_resp.gaf)) { 405 s_pmp_check := false.B 406 }.otherwise { 407 mem_addr_update := true.B 408 need_last_s2xlate := false.B 409 } 410 } 411 412 when(io.hptw.req.fire && s_last_hptw_req === false.B) { 413 w_last_hptw_resp := false.B 414 s_last_hptw_req := true.B 415 } 416 417 when (io.hptw.resp.fire && w_last_hptw_resp === false.B && stage1Hit){ 418 w_last_hptw_resp := true.B 419 hptw_resp_stage2 := true.B 420 hptw_resp := io.hptw.resp.bits.h_resp 421 } 422 423 when(io.hptw.resp.fire && w_last_hptw_resp === false.B && !stage1Hit){ 424 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf 425 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 426 hptw_resp := io.hptw.resp.bits.h_resp 427 w_last_hptw_resp := true.B 428 mem_addr_update := true.B 429 } 430 431 when(sent_to_pmp && mem_addr_update === false.B){ 432 s_mem_req := false.B 433 s_pmp_check := true.B 434 } 435 436 when(accessFault && idle === false.B){ 437 s_pmp_check := true.B 438 s_mem_req := true.B 439 w_mem_resp := true.B 440 s_llptw_req := true.B 441 s_hptw_req := true.B 442 w_hptw_resp := true.B 443 s_last_hptw_req := true.B 444 w_last_hptw_resp := true.B 445 mem_addr_update := true.B 446 need_last_s2xlate := false.B 447 if (HasBitmapCheck) { 448 s_bitmap_check := true.B 449 w_bitmap_resp := true.B 450 whether_need_bitmap_check := false.B 451 bitmap_checkfailed := false.B 452 } 453 } 454 455 when(guestFault && idle === false.B){ 456 s_pmp_check := true.B 457 s_mem_req := true.B 458 w_mem_resp := true.B 459 s_llptw_req := true.B 460 s_hptw_req := true.B 461 w_hptw_resp := true.B 462 s_last_hptw_req := true.B 463 w_last_hptw_resp := true.B 464 mem_addr_update := true.B 465 need_last_s2xlate := false.B 466 if (HasBitmapCheck) { 467 s_bitmap_check := true.B 468 w_bitmap_resp := true.B 469 whether_need_bitmap_check := false.B 470 bitmap_checkfailed := false.B 471 } 472 } 473 474 when (mem.req.fire){ 475 s_mem_req := true.B 476 w_mem_resp := false.B 477 } 478 479 when(mem.resp.fire && w_mem_resp === false.B){ 480 w_mem_resp := true.B 481 af_level := af_level - 1.U 482 gpf_level := Mux(mode === Sv39 && !pte_valid && !l2Hit, gpf_level - 2.U, gpf_level - 1.U) 483 pte_valid := true.B 484 update_full_gvpn_mem_resp := true.B 485 if (HasBitmapCheck) { 486 when (bitmap_enable) { 487 whether_need_bitmap_check := true.B 488 } .otherwise { 489 s_llptw_req := false.B 490 mem_addr_update := true.B 491 whether_need_bitmap_check := false.B 492 } 493 } else { 494 s_llptw_req := false.B 495 mem_addr_update := true.B 496 } 497 } 498 499 when(update_full_gvpn_mem_resp) { 500 update_full_gvpn_mem_resp := false.B 501 full_gvpn_reg := pte.getPPN() 502 } 503 504 if (HasBitmapCheck) { 505 when (whether_need_bitmap_check) { 506 when (bitmap_enable && (!enableS2xlate || onlyS1xlate) && pte.isLeaf()) { 507 s_bitmap_check := false.B 508 whether_need_bitmap_check := false.B 509 } .otherwise { 510 mem_addr_update := true.B 511 s_llptw_req := false.B 512 whether_need_bitmap_check := false.B 513 } 514 } 515 // bitmapcheck 516 when (io.bitmap.get.req.fire) { 517 s_bitmap_check := true.B 518 w_bitmap_resp := false.B 519 } 520 when (io.bitmap.get.resp.fire) { 521 w_bitmap_resp := true.B 522 mem_addr_update := true.B 523 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 524 } 525 } 526 527 when(mem_addr_update){ 528 when(level >= 2.U && !onlyS2xlate && !(guestFault || find_pte || accessFault)) { 529 level := levelNext 530 when(s2xlate){ 531 s_hptw_req := false.B 532 vs_finish := true.B 533 }.otherwise{ 534 s_mem_req := false.B 535 } 536 s_llptw_req := true.B 537 mem_addr_update := false.B 538 }.elsewhen(io.llptw.valid){ 539 when(io.llptw.fire) { 540 idle := true.B 541 s_llptw_req := true.B 542 mem_addr_update := false.B 543 need_last_s2xlate := false.B 544 } 545 finish := true.B 546 }.elsewhen(s2xlate && need_last_s2xlate === true.B) { 547 need_last_s2xlate := false.B 548 when(!(guestFault || accessFault || pageFault || ppn_af)){ 549 s_last_hptw_req := false.B 550 mem_addr_update := false.B 551 } 552 }.elsewhen(io.resp.valid){ 553 when(io.resp.fire) { 554 idle := true.B 555 s_llptw_req := true.B 556 mem_addr_update := false.B 557 accessFault := false.B 558 first_gvpn_check_fail := false.B 559 } 560 finish := true.B 561 } 562 } 563 564 565 when (flush) { 566 idle := true.B 567 s_pmp_check := true.B 568 s_mem_req := true.B 569 s_llptw_req := true.B 570 w_mem_resp := true.B 571 accessFault := false.B 572 mem_addr_update := false.B 573 first_gvpn_check_fail := false.B 574 s_hptw_req := true.B 575 w_hptw_resp := true.B 576 s_last_hptw_req := true.B 577 w_last_hptw_resp := true.B 578 if (HasBitmapCheck) { 579 s_bitmap_check := true.B 580 w_bitmap_resp := true.B 581 whether_need_bitmap_check := false.B 582 bitmap_checkfailed := false.B 583 } 584 } 585 586 587 XSDebug(p"[ptw] level:${level} notFound:${pageFault}\n") 588 589 // perf 590 XSPerfAccumulate("fsm_count", io.req.fire) 591 for (i <- 0 until PtwWidth) { 592 XSPerfAccumulate(s"fsm_count_source${i}", io.req.fire && io.req.bits.req_info.source === i.U) 593 } 594 XSPerfAccumulate("fsm_busy", !idle) 595 XSPerfAccumulate("fsm_idle", idle) 596 XSPerfAccumulate("resp_blocked", io.resp.valid && !io.resp.ready) 597 XSPerfAccumulate("ptw_ppn_af", io.resp.fire && ppn_af) 598 XSPerfAccumulate("mem_count", mem.req.fire) 599 XSPerfAccumulate("mem_cycle", BoolStopWatch(mem.req.fire, mem.resp.fire, true)) 600 XSPerfAccumulate("mem_blocked", mem.req.valid && !mem.req.ready) 601 602 val perfEvents = Seq( 603 ("fsm_count ", io.req.fire ), 604 ("fsm_busy ", !idle ), 605 ("fsm_idle ", idle ), 606 ("resp_blocked ", io.resp.valid && !io.resp.ready ), 607 ("mem_count ", mem.req.fire ), 608 ("mem_cycle ", BoolStopWatch(mem.req.fire, mem.resp.fire, true)), 609 ("mem_blocked ", mem.req.valid && !mem.req.ready ), 610 ) 611 generatePerfEvent() 612} 613 614/*========================= LLPTW ==============================*/ 615 616/** LLPTW : Last Level Page Table Walker 617 * the page walker that only takes 4KB(last level) page walk. 618 **/ 619 620class LLPTWInBundle(implicit p: Parameters) extends XSBundle with HasPtwConst { 621 val req_info = Output(new L2TlbInnerBundle()) 622 val ppn = Output(UInt(ptePPNLen.W)) 623 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 624 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 625 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 626 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 627 val hitway = UInt(l2tlbParams.l0nWays.W) 628 }) 629} 630 631class LLPTWIO(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 632 val in = Flipped(DecoupledIO(new LLPTWInBundle())) 633 val out = DecoupledIO(new Bundle { 634 val req_info = Output(new L2TlbInnerBundle()) 635 val id = Output(UInt(bMemID.W)) 636 val h_resp = Output(new HptwResp) 637 val first_s2xlate_fault = Output(Bool()) // Whether the first stage 2 translation occurs pf/af 638 val af = Output(Bool()) 639 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 640 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 641 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 642 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 643 }) 644 }) 645 val mem = new Bundle { 646 val req = DecoupledIO(new L2TlbMemReqBundle()) 647 val resp = Flipped(Valid(new Bundle { 648 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 649 val value = Output(UInt(blockBits.W)) 650 })) 651 val enq_ptr = Output(UInt(log2Ceil(l2tlbParams.llptwsize).W)) 652 val buffer_it = Output(Vec(l2tlbParams.llptwsize, Bool())) 653 val refill = Output(new L2TlbInnerBundle()) 654 val req_mask = Input(Vec(l2tlbParams.llptwsize, Bool())) 655 val flush_latch = Input(Vec(l2tlbParams.llptwsize, Bool())) 656 } 657 val cache = DecoupledIO(new L2TlbInnerBundle()) 658 val pmp = new Bundle { 659 val req = Valid(new PMPReqBundle()) 660 val resp = Flipped(new PMPRespBundle()) 661 } 662 val hptw = new Bundle { 663 val req = DecoupledIO(new Bundle{ 664 val source = UInt(bSourceWidth.W) 665 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 666 val gvpn = UInt(ptePPNLen.W) 667 }) 668 val resp = Flipped(Valid(new Bundle { 669 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 670 val h_resp = Output(new HptwResp) 671 })) 672 } 673 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 674 val req = DecoupledIO(new bitmapReqBundle()) 675 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 676 }) 677 678 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 679} 680 681class LLPTWEntry(implicit p: Parameters) extends XSBundle with HasPtwConst { 682 val req_info = new L2TlbInnerBundle() 683 val ppn = UInt(ptePPNLen.W) 684 val wait_id = UInt(log2Up(l2tlbParams.llptwsize).W) 685 val af = Bool() 686 val hptw_resp = new HptwResp() 687 val first_s2xlate_fault = Output(Bool()) 688 val cf = Bool() 689 val from_l0 = Bool() 690 val way_info = UInt(l2tlbParams.l0nWays.W) 691 val jmp_bitmap_check = Bool() 692 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) 693 val cfs = Vec(tlbcontiguous, Bool()) 694} 695 696 697class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 698 val io = IO(new LLPTWIO()) 699 700 // mbmc:bitmap csr 701 val mbmc = io.csr.mbmc 702 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 703 704 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 705 val entries = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(0.U.asTypeOf(new LLPTWEntry())))) 706 val state_idle :: state_hptw_req :: state_hptw_resp :: state_addr_check :: state_mem_req :: state_mem_waiting :: state_mem_out :: state_last_hptw_req :: state_last_hptw_resp :: state_cache :: state_bitmap_check :: state_bitmap_resp :: Nil = Enum(12) 707 val state = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(state_idle))) 708 709 val is_emptys = state.map(_ === state_idle) 710 val is_mems = state.map(_ === state_mem_req) 711 val is_waiting = state.map(_ === state_mem_waiting) 712 val is_having = state.map(_ === state_mem_out) 713 val is_cache = state.map(_ === state_cache) 714 val is_hptw_req = state.map(_ === state_hptw_req) 715 val is_last_hptw_req = state.map(_ === state_last_hptw_req) 716 val is_hptw_resp = state.map(_ === state_hptw_resp) 717 val is_last_hptw_resp = state.map(_ === state_last_hptw_resp) 718 val is_bitmap_req = state.map(_ === state_bitmap_check) 719 val is_bitmap_resp = state.map(_ === state_bitmap_resp) 720 721 val full = !ParallelOR(is_emptys).asBool 722 val enq_ptr = ParallelPriorityEncoder(is_emptys) 723 724 val mem_ptr = ParallelPriorityEncoder(is_having) // TODO: optimize timing, bad: entries -> ptr -> entry 725 val mem_arb = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 726 for (i <- 0 until l2tlbParams.llptwsize) { 727 mem_arb.io.in(i).bits := entries(i) 728 mem_arb.io.in(i).valid := is_mems(i) && !io.mem.req_mask(i) 729 } 730 731 // process hptw requests in serial 732 val hyper_arb1 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 733 for (i <- 0 until l2tlbParams.llptwsize) { 734 hyper_arb1.io.in(i).bits := entries(i) 735 hyper_arb1.io.in(i).valid := is_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 736 } 737 val hyper_arb2 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 738 for(i <- 0 until l2tlbParams.llptwsize) { 739 hyper_arb2.io.in(i).bits := entries(i) 740 hyper_arb2.io.in(i).valid := is_last_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 741 } 742 743 744 val bitmap_arb = Option.when(HasBitmapCheck)(Module(new RRArbiter(new bitmapReqBundle(), l2tlbParams.llptwsize))) 745 val way_info = Option.when(HasBitmapCheck)(Wire(Vec(l2tlbParams.llptwsize, UInt(l2tlbParams.l0nWays.W)))) 746 if (HasBitmapCheck) { 747 for (i <- 0 until l2tlbParams.llptwsize) { 748 bitmap_arb.get.io.in(i).valid := is_bitmap_req(i) 749 bitmap_arb.get.io.in(i).bits.bmppn := entries(i).ppn 750 bitmap_arb.get.io.in(i).bits.vpn := entries(i).req_info.vpn 751 bitmap_arb.get.io.in(i).bits.id := i.U 752 bitmap_arb.get.io.in(i).bits.level := 0.U // last level 753 bitmap_arb.get.io.in(i).bits.way_info := Mux(entries(i).from_l0, entries(i).way_info, way_info.get(i)) 754 bitmap_arb.get.io.in(i).bits.hptw_bypassed := false.B 755 } 756 } 757 758 val cache_ptr = ParallelMux(is_cache, (0 until l2tlbParams.llptwsize).map(_.U(log2Up(l2tlbParams.llptwsize).W))) 759 760 // duplicate req 761 // to_wait: wait for the last to access mem, set to mem_resp 762 // to_cache: the last is back just right now, set to mem_cache 763 val dup_vec = state.indices.map(i => 764 dup(io.in.bits.req_info.vpn, entries(i).req_info.vpn) && io.in.bits.req_info.s2xlate === entries(i).req_info.s2xlate 765 ) 766 val dup_req_fire = mem_arb.io.out.fire && dup(io.in.bits.req_info.vpn, mem_arb.io.out.bits.req_info.vpn) && io.in.bits.req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate // dup with the req fire entry 767 val dup_vec_wait = dup_vec.zip(is_waiting).map{case (d, w) => d && w} // dup with "mem_waiting" entries, sending mem req already 768 val dup_vec_having = dup_vec.zipWithIndex.map{case (d, i) => d && is_having(i)} // dup with the "mem_out" entry recv the data just now 769 val dup_vec_bitmap = dup_vec.zipWithIndex.map{case (d, i) => d && (is_bitmap_req(i) || is_bitmap_resp(i))} 770 val dup_vec_last_hptw = dup_vec.zipWithIndex.map{case (d, i) => d && (is_last_hptw_req(i) || is_last_hptw_resp(i))} 771 val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id))) 772 val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) && !io.mem.flush_latch(io.mem.resp.bits.id) // dup with the entry that data coming next cycle 773 val to_wait = Cat(dup_vec_wait).orR || dup_req_fire 774 val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && !bitmap_enable 775 val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && bitmap_enable 776 val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 777 else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 778 val to_hptw_req = io.in.bits.req_info.s2xlate === allStage 779 val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage 780 val last_hptw_req_id = io.mem.resp.bits.id 781 val req_paddr = MakeAddr(io.in.bits.ppn(ppnLen-1, 0), getVpnn(io.in.bits.req_info.vpn, 0)) 782 val req_hpaddr = MakeAddr(entries(last_hptw_req_id).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(io.in.bits.req_info.vpn, 0)) 783 val index = Mux(entries(last_hptw_req_id).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 784 val last_hptw_req_ppn = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index).getPPN() 785 XSError(RegNext(dup_req_fire && Cat(dup_vec_wait).orR, init = false.B), "mem req but some entries already waiting, should not happed") 786 787 XSError(io.in.fire && ((to_mem_out && to_cache) || (to_wait && to_cache)), "llptw enq, to cache conflict with to mem") 788 val mem_resp_hit = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(false.B))) 789 val enq_state_normal = MuxCase(state_addr_check, Seq( 790 to_mem_out -> state_mem_out, // same to the blew, but the mem resp now 791 to_bitmap_req -> state_bitmap_check, 792 to_last_hptw_req -> state_last_hptw_req, 793 to_wait -> state_mem_waiting, 794 to_cache -> state_cache, 795 to_hptw_req -> state_hptw_req 796 )) 797 val enq_state = Mux(from_pre(io.in.bits.req_info.source) && enq_state_normal =/= state_addr_check, state_idle, enq_state_normal) 798 when (io.in.fire && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 799 // if prefetch req does not need mem access, just give it up. 800 // so there will be at most 1 + FilterSize entries that needs re-access page cache 801 // so 2 + FilterSize is enough to avoid dead-lock 802 state(enq_ptr) := enq_state 803 entries(enq_ptr).req_info := io.in.bits.req_info 804 entries(enq_ptr).ppn := Mux(to_last_hptw_req, last_hptw_req_ppn, io.in.bits.ppn) 805 entries(enq_ptr).wait_id := Mux(to_wait, wait_id, enq_ptr) 806 entries(enq_ptr).af := false.B 807 if (HasBitmapCheck) { 808 entries(enq_ptr).cf := false.B 809 entries(enq_ptr).from_l0 := false.B 810 entries(enq_ptr).way_info := 0.U 811 entries(enq_ptr).jmp_bitmap_check := false.B 812 for (i <- 0 until tlbcontiguous) { 813 entries(enq_ptr).ptes(i) := 0.U 814 } 815 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 816 } 817 entries(enq_ptr).hptw_resp := Mux(to_last_hptw_req, entries(last_hptw_req_id).hptw_resp, Mux(to_wait, entries(wait_id).hptw_resp, entries(enq_ptr).hptw_resp)) 818 entries(enq_ptr).first_s2xlate_fault := false.B 819 mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req 820 } 821 822 if (HasBitmapCheck) { 823 when (io.in.bits.bitmapCheck.get.jmp_bitmap_check && io.in.fire) { 824 state(enq_ptr) := state_bitmap_check 825 entries(enq_ptr).req_info := io.in.bits.req_info 826 entries(enq_ptr).ppn := io.in.bits.bitmapCheck.get.ptes(io.in.bits.req_info.vpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType).ppn 827 entries(enq_ptr).wait_id := enq_ptr 828 entries(enq_ptr).af := false.B 829 entries(enq_ptr).cf := false.B 830 entries(enq_ptr).from_l0 := true.B 831 entries(enq_ptr).way_info := io.in.bits.bitmapCheck.get.hitway 832 entries(enq_ptr).jmp_bitmap_check := io.in.bits.bitmapCheck.get.jmp_bitmap_check 833 entries(enq_ptr).ptes := io.in.bits.bitmapCheck.get.ptes 834 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 835 mem_resp_hit(enq_ptr) := false.B 836 } 837 } 838 839 val enq_ptr_reg = RegNext(enq_ptr) 840 val need_addr_check = GatedValidRegNext(enq_state === state_addr_check && io.in.fire && !flush && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) 841 842 val hasHptwResp = ParallelOR(state.map(_ === state_hptw_resp)).asBool 843 val hptw_resp_ptr_reg = RegNext(io.hptw.resp.bits.id) 844 val hptw_need_addr_check = RegNext(hasHptwResp && io.hptw.resp.fire && !flush) && state(hptw_resp_ptr_reg) === state_addr_check 845 846 val ptes = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle())) 847 val gpaddr = MakeGPAddr(entries(hptw_resp_ptr_reg).ppn, getVpnn(entries(hptw_resp_ptr_reg).req_info.vpn, 0)) 848 val hptw_resp = entries(hptw_resp_ptr_reg).hptw_resp 849 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 850 val addr = RegEnable(MakeAddr(io.in.bits.ppn(ppnLen - 1, 0), getVpnn(io.in.bits.req_info.vpn, 0)), io.in.fire) 851 io.pmp.req.valid := need_addr_check || hptw_need_addr_check 852 io.pmp.req.bits.addr := Mux(hptw_need_addr_check, hpaddr, addr) 853 io.pmp.req.bits.cmd := TlbCmd.read 854 io.pmp.req.bits.size := 3.U // TODO: fix it 855 val pmp_resp_valid = io.pmp.req.valid // same cycle 856 when (pmp_resp_valid) { 857 // NOTE: when pmp resp but state is not addr check, then the entry is dup with other entry, the state was changed before 858 // when dup with the req-ing entry, set to mem_waiting (above codes), and the ld must be false, so dontcare 859 val ptr = Mux(hptw_need_addr_check, hptw_resp_ptr_reg, enq_ptr_reg); 860 val accessFault = io.pmp.resp.ld || io.pmp.resp.mmio 861 entries(ptr).af := accessFault 862 state(ptr) := Mux(accessFault, state_mem_out, state_mem_req) 863 } 864 865 when (mem_arb.io.out.fire) { 866 for (i <- state.indices) { 867 when (state(i) =/= state_idle && state(i) =/= state_mem_out && state(i) =/= state_last_hptw_req && state(i) =/= state_last_hptw_resp 868 && (if (HasBitmapCheck) state(i) =/= state_bitmap_check && state(i) =/= state_bitmap_resp else true.B) 869 && entries(i).req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate 870 && dup(entries(i).req_info.vpn, mem_arb.io.out.bits.req_info.vpn)) { 871 // NOTE: "dup enq set state to mem_wait" -> "sending req set other dup entries to mem_wait" 872 state(i) := state_mem_waiting 873 entries(i).hptw_resp := entries(mem_arb.io.chosen).hptw_resp 874 entries(i).wait_id := mem_arb.io.chosen 875 } 876 } 877 } 878 when (io.mem.resp.fire) { 879 state.indices.map{i => 880 when (state(i) === state_mem_waiting && io.mem.resp.bits.id === entries(i).wait_id) { 881 val req_paddr = MakeAddr(entries(i).ppn, getVpnn(entries(i).req_info.vpn, 0)) 882 val req_hpaddr = MakeAddr(entries(i).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(entries(i).req_info.vpn, 0)) 883 val index = Mux(entries(i).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 884 val enableS2xlate = entries(i).req_info.s2xlate =/= noS2xlate 885 val s1Pbmte = Mux(enableS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 886 val vsStagePf = ptes(index).isPf(0.U, s1Pbmte) || !ptes(index).isLeaf() // Pagefault in vs-Stage 887 // Pagefault in g-Stage; when vsStagePf valid, should not check gStagepf 888 val gStagePf = ptes(index).isStage1Gpf(io.csr.hgatp.mode) && !vsStagePf 889 state(i) := Mux(entries(i).req_info.s2xlate === allStage && !(vsStagePf || gStagePf), 890 state_last_hptw_req, 891 Mux(bitmap_enable, state_bitmap_check, state_mem_out)) 892 mem_resp_hit(i) := true.B 893 entries(i).ppn := Mux(ptes(index).n === 0.U, ptes(index).getPPN(), Cat(ptes(index).getPPN()(ptePPNLen - 1, pteNapotBits), entries(i).req_info.vpn(pteNapotBits - 1, 0))) // for last stage 2 translation 894 // af will be judged in L2 TLB `contiguous_pte_to_merge_ptwResp` 895 entries(i).hptw_resp.gpf := Mux(entries(i).req_info.s2xlate === allStage, gStagePf, false.B) 896 } 897 } 898 } 899 900 if (HasBitmapCheck) { 901 for (i <- 0 until l2tlbParams.llptwsize) { 902 way_info.get(i) := DataHoldBypass(io.l0_way_info.get, mem_resp_hit(i)) 903 } 904 } 905 906 when (hyper_arb1.io.out.fire) { 907 for (i <- state.indices) { 908 when (state(i) === state_hptw_req && entries(i).ppn === hyper_arb1.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb1.io.chosen === i.U) { 909 state(i) := state_hptw_resp 910 entries(i).wait_id := hyper_arb1.io.chosen 911 } 912 } 913 } 914 915 when (hyper_arb2.io.out.fire) { 916 for (i <- state.indices) { 917 when (state(i) === state_last_hptw_req && entries(i).ppn === hyper_arb2.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb2.io.chosen === i.U) { 918 state(i) := state_last_hptw_resp 919 entries(i).wait_id := hyper_arb2.io.chosen 920 } 921 } 922 } 923 924 if (HasBitmapCheck) { 925 when (bitmap_arb.get.io.out.fire) { 926 for (i <- state.indices) { 927 when (is_bitmap_req(i) && bitmap_arb.get.io.out.bits.bmppn === entries(i).ppn(ppnLen - 1, 0)) { 928 state(i) := state_bitmap_resp 929 entries(i).wait_id := bitmap_arb.get.io.chosen 930 } 931 } 932 } 933 934 when (io.bitmap.get.resp.fire) { 935 for (i <- state.indices) { 936 when (is_bitmap_resp(i) && io.bitmap.get.resp.bits.id === entries(i).wait_id) { 937 entries(i).cfs := io.bitmap.get.resp.bits.cfs 938 entries(i).cf := io.bitmap.get.resp.bits.cf 939 state(i) := state_mem_out 940 } 941 } 942 } 943 } 944 945 when (io.hptw.resp.fire) { 946 for (i <- state.indices) { 947 when (state(i) === state_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 948 val check_g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 949 when (check_g_perm_fail || io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf) { 950 state(i) := state_mem_out 951 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 952 entries(i).hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || check_g_perm_fail 953 entries(i).first_s2xlate_fault := io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf 954 }.otherwise{ // change the entry that is waiting hptw resp 955 val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting && dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn)) 956 val waiting_index = ParallelMux(need_to_waiting_vec zip entries.map(_.wait_id)) 957 state(i) := Mux(Cat(need_to_waiting_vec).orR, state_mem_waiting, state_addr_check) 958 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 959 entries(i).wait_id := Mux(Cat(need_to_waiting_vec).orR, waiting_index, entries(i).wait_id) 960 //To do: change the entry that is having the same hptw req 961 } 962 } 963 when (state(i) === state_last_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 964 state(i) := state_mem_out 965 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 966 //To do: change the entry that is having the same hptw req 967 } 968 } 969 } 970 when (io.out.fire) { 971 assert(state(mem_ptr) === state_mem_out) 972 state(mem_ptr) := state_idle 973 } 974 mem_resp_hit.map(a => when (a) { a := false.B } ) 975 976 when (io.cache.fire) { 977 state(cache_ptr) := state_idle 978 } 979 XSError(io.out.fire && io.cache.fire && (mem_ptr === cache_ptr), "mem resp and cache fire at the same time at same entry") 980 981 when (flush) { 982 state.map(_ := state_idle) 983 } 984 985 io.in.ready := !full 986 987 io.out.valid := ParallelOR(is_having).asBool 988 io.out.bits.req_info := entries(mem_ptr).req_info 989 io.out.bits.id := mem_ptr 990 if (HasBitmapCheck) { 991 io.out.bits.af := Mux(bitmap_enable, entries(mem_ptr).af || entries(mem_ptr).cf, entries(mem_ptr).af) 992 io.out.bits.bitmapCheck.get.jmp_bitmap_check := entries(mem_ptr).jmp_bitmap_check 993 io.out.bits.bitmapCheck.get.ptes := entries(mem_ptr).ptes 994 io.out.bits.bitmapCheck.get.cfs := entries(mem_ptr).cfs 995 } else { 996 io.out.bits.af := entries(mem_ptr).af 997 } 998 999 io.out.bits.h_resp := entries(mem_ptr).hptw_resp 1000 io.out.bits.first_s2xlate_fault := entries(mem_ptr).first_s2xlate_fault 1001 1002 val hptw_req_arb = Module(new Arbiter(new Bundle{ 1003 val source = UInt(bSourceWidth.W) 1004 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1005 val ppn = UInt(ptePPNLen.W) 1006 } , 2)) 1007 // first stage 2 translation 1008 hptw_req_arb.io.in(0).valid := hyper_arb1.io.out.valid 1009 hptw_req_arb.io.in(0).bits.source := hyper_arb1.io.out.bits.req_info.source 1010 hptw_req_arb.io.in(0).bits.ppn := hyper_arb1.io.out.bits.ppn 1011 hptw_req_arb.io.in(0).bits.id := hyper_arb1.io.chosen 1012 hyper_arb1.io.out.ready := hptw_req_arb.io.in(0).ready 1013 // last stage 2 translation 1014 hptw_req_arb.io.in(1).valid := hyper_arb2.io.out.valid 1015 hptw_req_arb.io.in(1).bits.source := hyper_arb2.io.out.bits.req_info.source 1016 hptw_req_arb.io.in(1).bits.ppn := hyper_arb2.io.out.bits.ppn 1017 hptw_req_arb.io.in(1).bits.id := hyper_arb2.io.chosen 1018 hyper_arb2.io.out.ready := hptw_req_arb.io.in(1).ready 1019 hptw_req_arb.io.out.ready := io.hptw.req.ready 1020 io.hptw.req.valid := hptw_req_arb.io.out.fire && !flush 1021 io.hptw.req.bits.gvpn := hptw_req_arb.io.out.bits.ppn 1022 io.hptw.req.bits.id := hptw_req_arb.io.out.bits.id 1023 io.hptw.req.bits.source := hptw_req_arb.io.out.bits.source 1024 1025 io.mem.req.valid := mem_arb.io.out.valid && !flush 1026 val mem_paddr = MakeAddr(mem_arb.io.out.bits.ppn, getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1027 val mem_hpaddr = MakeAddr(mem_arb.io.out.bits.hptw_resp.genPPNS2(get_pn(mem_paddr)), getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1028 io.mem.req.bits.addr := Mux(mem_arb.io.out.bits.req_info.s2xlate === allStage, mem_hpaddr, mem_paddr) 1029 io.mem.req.bits.id := mem_arb.io.chosen 1030 io.mem.req.bits.hptw_bypassed := false.B 1031 mem_arb.io.out.ready := io.mem.req.ready 1032 val mem_refill_id = RegNext(io.mem.resp.bits.id(log2Up(l2tlbParams.llptwsize)-1, 0)) 1033 io.mem.refill := entries(mem_refill_id).req_info 1034 io.mem.refill.s2xlate := entries(mem_refill_id).req_info.s2xlate 1035 io.mem.buffer_it := mem_resp_hit 1036 io.mem.enq_ptr := enq_ptr 1037 1038 io.cache.valid := Cat(is_cache).orR 1039 io.cache.bits := ParallelMux(is_cache, entries.map(_.req_info)) 1040 1041 val has_bitmap_resp = ParallelOR(is_bitmap_resp).asBool 1042 if (HasBitmapCheck) { 1043 io.bitmap.get.req.valid := bitmap_arb.get.io.out.valid && !flush 1044 io.bitmap.get.req.bits.bmppn := bitmap_arb.get.io.out.bits.bmppn 1045 io.bitmap.get.req.bits.id := bitmap_arb.get.io.chosen 1046 io.bitmap.get.req.bits.vpn := bitmap_arb.get.io.out.bits.vpn 1047 io.bitmap.get.req.bits.level := 0.U 1048 io.bitmap.get.req.bits.way_info := bitmap_arb.get.io.out.bits.way_info 1049 io.bitmap.get.req.bits.hptw_bypassed := bitmap_arb.get.io.out.bits.hptw_bypassed 1050 bitmap_arb.get.io.out.ready := io.bitmap.get.req.ready 1051 io.bitmap.get.resp.ready := has_bitmap_resp 1052 } 1053 1054 XSPerfAccumulate("llptw_in_count", io.in.fire) 1055 XSPerfAccumulate("llptw_in_block", io.in.valid && !io.in.ready) 1056 for (i <- 0 until 7) { 1057 XSPerfAccumulate(s"enq_state${i}", io.in.fire && enq_state === i.U) 1058 } 1059 for (i <- 0 until (l2tlbParams.llptwsize + 1)) { 1060 XSPerfAccumulate(s"util${i}", PopCount(is_emptys.map(!_)) === i.U) 1061 XSPerfAccumulate(s"mem_util${i}", PopCount(is_mems) === i.U) 1062 XSPerfAccumulate(s"waiting_util${i}", PopCount(is_waiting) === i.U) 1063 } 1064 XSPerfAccumulate("mem_count", io.mem.req.fire) 1065 XSPerfAccumulate("mem_cycle", PopCount(is_waiting) =/= 0.U) 1066 XSPerfAccumulate("blocked_in", io.in.valid && !io.in.ready) 1067 1068 val perfEvents = Seq( 1069 ("tlbllptw_incount ", io.in.fire ), 1070 ("tlbllptw_inblock ", io.in.valid && !io.in.ready), 1071 ("tlbllptw_memcount ", io.mem.req.fire ), 1072 ("tlbllptw_memcycle ", PopCount(is_waiting) ), 1073 ) 1074 generatePerfEvent() 1075} 1076 1077/*========================= HPTW ==============================*/ 1078 1079/** HPTW : Hypervisor Page Table Walker 1080 * the page walker take the virtual machine's page walk. 1081 * guest physical address translation, guest physical address -> host physical address 1082 **/ 1083class HPTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 1084 val req = Flipped(DecoupledIO(new Bundle { 1085 val source = UInt(bSourceWidth.W) 1086 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1087 val gvpn = UInt(gvpnLen.W) 1088 val ppn = UInt(ppnLen.W) 1089 val l3Hit = if (EnableSv48) Some(new Bool()) else None 1090 val l2Hit = Bool() 1091 val l1Hit = Bool() 1092 val bypassed = Bool() // if bypass, don't refill 1093 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 1094 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 1095 val pte = UInt(XLEN.W) // Page Table Entry 1096 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 1097 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 1098 val hitway = UInt(l2tlbParams.l0nWays.W) 1099 val fromSP = Bool() 1100 val SPlevel = UInt(log2Up(Level).W) 1101 }) 1102 })) 1103 val resp = DecoupledIO(new Bundle { 1104 val source = UInt(bSourceWidth.W) 1105 val resp = Output(new HptwResp()) 1106 val id = Output(UInt(bMemID.W)) 1107 }) 1108 1109 val mem = new Bundle { 1110 val req = DecoupledIO(new L2TlbMemReqBundle()) 1111 val resp = Flipped(ValidIO(UInt(XLEN.W))) 1112 val mask = Input(Bool()) 1113 } 1114 val refill = Output(new Bundle { 1115 val req_info = new L2TlbInnerBundle() 1116 val level = UInt(log2Up(Level + 1).W) 1117 }) 1118 val pmp = new Bundle { 1119 val req = ValidIO(new PMPReqBundle()) 1120 val resp = Flipped(new PMPRespBundle()) 1121 } 1122 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 1123 val req = DecoupledIO(new bitmapReqBundle()) 1124 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 1125 }) 1126 1127 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 1128} 1129 1130class HPTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 1131 val io = IO(new HPTWIO) 1132 val hgatp = io.csr.hgatp 1133 val mpbmte = io.csr.mPBMTE 1134 val sfence = io.sfence 1135 val flush = sfence.valid || hgatp.changed || io.csr.satp.changed || io.csr.vsatp.changed 1136 val mode = hgatp.mode 1137 1138 // mbmc:bitmap csr 1139 val mbmc = io.csr.mbmc 1140 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 1141 1142 val level = RegInit(3.U(log2Up(Level + 1).W)) 1143 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 1144 val gpaddr = Reg(UInt(GPAddrBits.W)) 1145 val req_ppn = Reg(UInt(ppnLen.W)) 1146 val vpn = gpaddr(GPAddrBits-1, offLen) 1147 val levelNext = level - 1.U 1148 val l3Hit = Reg(Bool()) 1149 val l2Hit = Reg(Bool()) 1150 val l1Hit = Reg(Bool()) 1151 val bypassed = Reg(Bool()) 1152// val pte = io.mem.resp.bits.MergeRespToPte() 1153 val jmp_bitmap_check = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.jmp_bitmap_check, io.req.fire) else false.B 1154 val fromSP = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.fromSP, io.req.fire) else false.B 1155 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.bits.bitmapCheck.get.ptes(io.req.bits.gvpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType)), io.req.fire)) 1156 val pte = if (HasBitmapCheck) Mux(jmp_bitmap_check, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) else io.mem.resp.bits.asTypeOf(new PteBundle().cloneType) 1157 val ppn_l3 = Mux(l3Hit, req_ppn, pte.ppn) 1158 val ppn_l2 = Mux(l2Hit, req_ppn, pte.ppn) 1159 val ppn_l1 = Mux(l1Hit, req_ppn, pte.ppn) 1160 val ppn = Wire(UInt(PAddrBits.W)) 1161 val p_pte = MakeAddr(ppn, getVpnn(vpn, level)) 1162 val pg_base = Wire(UInt(PAddrBits.W)) 1163 val mem_addr = Wire(UInt(PAddrBits.W)) 1164 if (EnableSv48) { 1165 when (mode === Sv48) { 1166 ppn := Mux(af_level === 2.U, ppn_l3, Mux(af_level === 1.U, ppn_l2, ppn_l1)) // for l2, l1 and l3 1167 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 3.U, mode = Sv48)) // for l3 1168 mem_addr := Mux(af_level === 3.U, pg_base, p_pte) 1169 } .otherwise { 1170 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1171 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1172 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1173 } 1174 } else { 1175 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1176 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1177 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1178 } 1179 1180 //s/w register 1181 val s_pmp_check = RegInit(true.B) 1182 val s_mem_req = RegInit(true.B) 1183 val w_mem_resp = RegInit(true.B) 1184 val idle = RegInit(true.B) 1185 val mem_addr_update = RegInit(false.B) 1186 val finish = WireInit(false.B) 1187 val s_bitmap_check = RegInit(true.B) 1188 val w_bitmap_resp = RegInit(true.B) 1189 val whether_need_bitmap_check = RegInit(false.B) 1190 val bitmap_checkfailed = RegInit(false.B) 1191 1192 val sent_to_pmp = !idle && (!s_pmp_check || mem_addr_update) && !finish 1193 val pageFault = pte.isGpf(level, mpbmte) || (!pte.isLeaf() && level === 0.U) 1194 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, sent_to_pmp) 1195 1196 // use access fault when bitmap check failed 1197 val ppn_af = if (HasBitmapCheck) { 1198 Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 1199 } else { 1200 pte.isAf() 1201 } 1202 val find_pte = pte.isLeaf() || ppn_af || pageFault 1203 1204 val resp_valid = !idle && mem_addr_update && ((w_mem_resp && find_pte) || (s_pmp_check && accessFault)) 1205 val id = Reg(UInt(log2Up(l2tlbParams.llptwsize).W)) 1206 val source = RegEnable(io.req.bits.source, io.req.fire) 1207 1208 io.req.ready := idle 1209 val resp = Wire(new HptwResp()) 1210 // accessFault > pageFault > ppn_af 1211 resp.apply( 1212 gpf = pageFault && !accessFault, 1213 gaf = accessFault || (ppn_af && !pageFault), 1214 level = Mux(accessFault, af_level, level), 1215 pte = pte, 1216 vpn = vpn, 1217 vmid = hgatp.vmid 1218 ) 1219 io.resp.valid := resp_valid 1220 io.resp.bits.id := id 1221 io.resp.bits.resp := resp 1222 io.resp.bits.source := source 1223 1224 io.pmp.req.valid := DontCare 1225 io.pmp.req.bits.addr := mem_addr 1226 io.pmp.req.bits.size := 3.U 1227 io.pmp.req.bits.cmd := TlbCmd.read 1228 1229 if (HasBitmapCheck) { 1230 val way_info = DataHoldBypass(io.l0_way_info.get, RegNext(io.mem.resp.fire, init=false.B)) 1231 val cache_hitway = RegEnable(io.req.bits.bitmapCheck.get.hitway, io.req.fire) 1232 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 1233 io.bitmap.get.req.valid := !s_bitmap_check 1234 io.bitmap.get.req.bits.bmppn := pte.ppn 1235 io.bitmap.get.req.bits.id := HptwReqId.U(bMemID.W) 1236 io.bitmap.get.req.bits.vpn := vpn 1237 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check, Mux(fromSP,cache_level,0.U), level) 1238 io.bitmap.get.req.bits.way_info := Mux(jmp_bitmap_check, cache_hitway, way_info) 1239 io.bitmap.get.req.bits.hptw_bypassed := bypassed 1240 io.bitmap.get.resp.ready := !w_bitmap_resp 1241 } 1242 1243 io.mem.req.valid := !s_mem_req && !io.mem.mask && !accessFault && s_pmp_check 1244 io.mem.req.bits.addr := mem_addr 1245 io.mem.req.bits.id := HptwReqId.U(bMemID.W) 1246 io.mem.req.bits.hptw_bypassed := bypassed 1247 1248 io.refill.req_info.vpn := vpn 1249 io.refill.level := level 1250 io.refill.req_info.source := source 1251 io.refill.req_info.s2xlate := onlyStage2 1252 1253 when (idle){ 1254 if (HasBitmapCheck) { 1255 when (io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.fire) { 1256 idle := false.B 1257 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1258 s_bitmap_check := false.B 1259 id := io.req.bits.id 1260 level := Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.SPlevel, 0.U) 1261 } 1262 } 1263 when (io.req.fire && (if (HasBitmapCheck) !io.req.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 1264 bypassed := io.req.bits.bypassed 1265 idle := false.B 1266 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1267 accessFault := false.B 1268 s_pmp_check := false.B 1269 id := io.req.bits.id 1270 req_ppn := io.req.bits.ppn 1271 if (EnableSv48) { 1272 when (mode === Sv48) { 1273 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1274 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1275 l3Hit := io.req.bits.l3Hit.get 1276 } .otherwise { 1277 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1278 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1279 l3Hit := false.B 1280 } 1281 } else { 1282 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1283 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1284 l3Hit := false.B 1285 } 1286 l2Hit := io.req.bits.l2Hit 1287 l1Hit := io.req.bits.l1Hit 1288 } 1289 } 1290 1291 when(sent_to_pmp && !mem_addr_update){ 1292 s_mem_req := false.B 1293 s_pmp_check := true.B 1294 } 1295 1296 when(accessFault && !idle){ 1297 s_pmp_check := true.B 1298 s_mem_req := true.B 1299 w_mem_resp := true.B 1300 mem_addr_update := true.B 1301 if (HasBitmapCheck) { 1302 s_bitmap_check := true.B 1303 w_bitmap_resp := true.B 1304 whether_need_bitmap_check := false.B 1305 bitmap_checkfailed := false.B 1306 } 1307 } 1308 1309 when(io.mem.req.fire){ 1310 s_mem_req := true.B 1311 w_mem_resp := false.B 1312 } 1313 1314 when(io.mem.resp.fire && !w_mem_resp){ 1315 w_mem_resp := true.B 1316 af_level := af_level - 1.U 1317 if (HasBitmapCheck) { 1318 when (bitmap_enable) { 1319 whether_need_bitmap_check := true.B 1320 } .otherwise { 1321 mem_addr_update := true.B 1322 whether_need_bitmap_check := false.B 1323 } 1324 } else { 1325 mem_addr_update := true.B 1326 } 1327 } 1328 1329 if (HasBitmapCheck) { 1330 when (whether_need_bitmap_check) { 1331 when (bitmap_enable && pte.isLeaf()) { 1332 s_bitmap_check := false.B 1333 whether_need_bitmap_check := false.B 1334 } .otherwise { 1335 mem_addr_update := true.B 1336 whether_need_bitmap_check := false.B 1337 } 1338 } 1339 // bitmapcheck 1340 when (io.bitmap.get.req.fire) { 1341 s_bitmap_check := true.B 1342 w_bitmap_resp := false.B 1343 } 1344 when (io.bitmap.get.resp.fire) { 1345 w_bitmap_resp := true.B 1346 mem_addr_update := true.B 1347 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 1348 } 1349 } 1350 1351 when(mem_addr_update){ 1352 when(!(find_pte || accessFault)){ 1353 level := levelNext 1354 s_mem_req := false.B 1355 mem_addr_update := false.B 1356 }.elsewhen(resp_valid){ 1357 when(io.resp.fire){ 1358 idle := true.B 1359 mem_addr_update := false.B 1360 accessFault := false.B 1361 } 1362 finish := true.B 1363 } 1364 } 1365 when (flush) { 1366 idle := true.B 1367 s_pmp_check := true.B 1368 s_mem_req := true.B 1369 w_mem_resp := true.B 1370 accessFault := false.B 1371 mem_addr_update := false.B 1372 if (HasBitmapCheck) { 1373 s_bitmap_check := true.B 1374 w_bitmap_resp := true.B 1375 whether_need_bitmap_check := false.B 1376 bitmap_checkfailed := false.B 1377 } 1378 } 1379} 1380