1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import chisel3.internal.naming.chiselName 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31 32class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 33 34 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 35 clients = Seq(TLMasterParameters.v1( 36 "ptw", 37 sourceId = IdRange(0, MemReqWidth) 38 )) 39 ))) 40 41 lazy val module = new L2TLBImp(this) 42} 43 44@chiselName 45class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 46 47 val (mem, edge) = outer.node.out.head 48 49 val io = IO(new L2TLBIO) 50 val difftestIO = IO(new Bundle() { 51 val ptwResp = Output(Bool()) 52 val ptwAddr = Output(UInt(64.W)) 53 val ptwData = Output(Vec(4, UInt(64.W))) 54 }) 55 56 /* Ptw processes multiple requests 57 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 58 * miss queue itlb dtlb 59 * | | | 60 * ------arbiter------ 61 * | 62 * l1 - l2 - l3 - sp 63 * | 64 * ------------------------------------------- 65 * miss | queue | hit 66 * [][][][][][] | 67 * | | 68 * state machine accessing mem | 69 * | | 70 * ---------------arbiter--------------------- 71 * | | 72 * itlb dtlb 73 */ 74 75 difftestIO <> DontCare 76 77 val sfence_tmp = DelayN(io.sfence, 1) 78 val csr_tmp = DelayN(io.csr.tlb, 1) 79 val sfence_dup = Seq.fill(8)(RegNext(sfence_tmp)) 80 val csr_dup = Seq.fill(7)(RegNext(csr_tmp)) 81 val satp = csr_dup(0).satp 82 val priv = csr_dup(0).priv 83 val flush = sfence_dup(0).valid || satp.changed 84 85 val pmp = Module(new PMP()) 86 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 87 pmp.io.distribute_csr := io.csr.distribute_csr 88 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 89 90 val missQueue = Module(new L2TlbMissQueue) 91 val cache = Module(new PtwCache) 92 val ptw = Module(new PTW) 93 val llptw = Module(new LLPTW) 94 val blockmq = Module(new BlockHelper(3)) 95 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 96 val arb2 = Module(new Arbiter(new Bundle { 97 val vpn = UInt(vpnLen.W) 98 val source = UInt(bSourceWidth.W) 99 }, if (l2tlbParams.enablePrefetch) 4 else 3)) 100 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new PtwResp, 3)).io) 101 val outArbCachePort = 0 102 val outArbFsmPort = 1 103 val outArbMqPort = 2 104 105 // arb2 input port 106 val InArbPTWPort = 0 107 val InArbMissQueuePort = 1 108 val InArbTlbPort = 2 109 val InArbPrefetchPort = 3 110 // NOTE: when cache out but miss and ptw doesnt accept, 111 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 112 arb1.io.out.ready := arb2.io.in(InArbTlbPort).ready 113 114 arb2.io.in(InArbPTWPort).valid := ptw.io.llptw.valid 115 arb2.io.in(InArbPTWPort).bits.vpn := ptw.io.llptw.bits.req_info.vpn 116 arb2.io.in(InArbPTWPort).bits.source := ptw.io.llptw.bits.req_info.source 117 ptw.io.llptw.ready := arb2.io.in(InArbPTWPort).ready 118 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 119 120 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 121 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 122 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 123 if (l2tlbParams.enablePrefetch) { 124 val prefetch = Module(new L2TlbPrefetch()) 125 val recv = cache.io.resp 126 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 127 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 128 prefetch.io.in.valid := recv.fire() && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 129 recv.bits.prefetch) && recv.bits.isFirst 130 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 131 prefetch.io.sfence := sfence_dup(0) 132 prefetch.io.csr := csr_dup(0) 133 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 134 } 135 arb2.io.out.ready := cache.io.req.ready 136 137 138 val mq_arb = Module(new Arbiter(new L2TlbInnerBundle, 2)) 139 mq_arb.io.in(0).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 140 (!cache.io.resp.bits.toFsm.l2Hit || cache.io.resp.bits.bypassed) && 141 !from_pre(cache.io.resp.bits.req_info.source) && 142 (cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst || !ptw.io.req.ready) 143 mq_arb.io.in(0).bits := cache.io.resp.bits.req_info 144 mq_arb.io.in(1) <> llptw.io.cache 145 missQueue.io.in <> mq_arb.io.out 146 missQueue.io.sfence := sfence_dup(6) 147 missQueue.io.csr := csr_dup(5) 148 149 blockmq.io.start := missQueue.io.out.fire 150 blockmq.io.enable := ptw.io.req.fire() 151 152 llptw.io.in.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed 153 llptw.io.in.bits.req_info := cache.io.resp.bits.req_info 154 llptw.io.in.bits.ppn := cache.io.resp.bits.toFsm.ppn 155 llptw.io.sfence := sfence_dup(1) 156 llptw.io.csr := csr_dup(1) 157 158 cache.io.req.valid := arb2.io.out.valid 159 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 160 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 161 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 162 cache.io.req.bits.bypassed.map(_ := false.B) 163 cache.io.sfence := sfence_dup(2) 164 cache.io.csr := csr_dup(2) 165 cache.io.sfence_dup.zip(sfence_dup.drop(2).take(4)).map(s => s._1 := s._2) 166 cache.io.csr_dup.zip(csr_dup.drop(2).take(3)).map(c => c._1 := c._2) 167 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 168 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 169 Mux(cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed, llptw.io.in.ready, 170 Mux(cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst, mq_arb.io.in(0).ready, mq_arb.io.in(0).ready || ptw.io.req.ready))) 171 172 // NOTE: missQueue req has higher priority 173 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit && 174 !cache.io.resp.bits.bypassed && 175 !cache.io.resp.bits.isFirst 176 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 177 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 178 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 179 ptw.io.sfence := sfence_dup(7) 180 ptw.io.csr := csr_dup(6) 181 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 182 183 // mem req 184 def blockBytes_align(addr: UInt) = { 185 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 186 } 187 def addr_low_from_vpn(vpn: UInt) = { 188 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 189 } 190 def addr_low_from_paddr(paddr: UInt) = { 191 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 192 } 193 def from_missqueue(id: UInt) = { 194 (id =/= l2tlbParams.llptwsize.U) 195 } 196 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 197 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 198 for (i <- waiting_resp.indices) { 199 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 200 } 201 202 val llptw_out = llptw.io.out 203 val llptw_mem = llptw.io.mem 204 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 205 ptw.io.mem.mask := waiting_resp.last 206 207 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 2)) 208 mem_arb.io.in(0) <> ptw.io.mem.req 209 mem_arb.io.in(1) <> llptw_mem.req 210 mem_arb.io.out.ready := mem.a.ready && !flush 211 212 // assert, should not send mem access at same addr for twice. 213 val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info_dup(0).vpn, cache.io.refill.valid) 214 val last_resp_level = RegEnable(cache.io.refill.bits.level_dup(0), cache.io.refill.valid) 215 val last_resp_v = RegInit(false.B) 216 val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR 217 when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 218 when (flush) { last_resp_v := false.B } 219 XSError(last_resp_v && cache.io.refill.valid && 220 (cache.io.refill.bits.req_info_dup(0).vpn === last_resp_vpn) && 221 (cache.io.refill.bits.level_dup(0) === last_resp_level), 222 "l2tlb should not access mem at same addr for twice") 223 // ATTENTION: this may wronngly assert when: a ptes is l2, last part is valid, 224 // but the current part is invalid, so one more mem access happened 225 // If this happened, remove the assert. 226 227 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 228 229 when (llptw.io.in.fire()) { 230 // when enq miss queue, set the req_addr_low to receive the mem resp data part 231 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 232 } 233 when (mem_arb.io.out.fire()) { 234 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 235 waiting_resp(mem_arb.io.out.bits.id) := true.B 236 } 237 // mem read 238 val memRead = edge.Get( 239 fromSource = mem_arb.io.out.bits.id, 240 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 241 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 242 lgSize = log2Up(l2tlbParams.blockBytes).U 243 )._2 244 mem.a.bits := memRead 245 mem.a.valid := mem_arb.io.out.valid && !flush 246 mem.d.ready := true.B 247 // mem -> data buffer 248 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 249 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire()) 250 val mem_resp_done = refill_helper._3 251 val mem_resp_from_mq = from_missqueue(mem.d.bits.source) 252 when (mem.d.valid) { 253 assert(mem.d.bits.source <= l2tlbParams.llptwsize.U) 254 refill_data(refill_helper._4) := mem.d.bits.data 255 } 256 // refill_data_tmp is the wire fork of refill_data, but one cycle earlier 257 val refill_data_tmp = WireInit(refill_data) 258 refill_data_tmp(refill_helper._4) := mem.d.bits.data 259 260 // save only one pte for each id 261 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 262 val resp_pte = VecInit((0 until MemReqWidth).map(i => 263 if (i == l2tlbParams.llptwsize) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && !mem_resp_from_mq) } 264 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 265 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 266 )) 267 268 // mem -> miss queue 269 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_mq 270 llptw_mem.resp.bits.id := DataHoldBypass(mem.d.bits.source, mem.d.valid) 271 // mem -> ptw 272 ptw.io.mem.req.ready := mem.a.ready 273 ptw.io.mem.resp.valid := mem_resp_done && !mem_resp_from_mq 274 ptw.io.mem.resp.bits := resp_pte.last 275 // mem -> cache 276 val refill_from_mq = mem_resp_from_mq 277 val refill_level = Mux(refill_from_mq, 2.U, RegEnable(ptw.io.refill.level, init = 0.U, ptw.io.mem.req.fire())) 278 val refill_valid = mem_resp_done && !flush && !flush_latch(mem.d.bits.source) 279 280 cache.io.refill.valid := RegNext(refill_valid, false.B) 281 cache.io.refill.bits.ptes := refill_data.asUInt 282 cache.io.refill.bits.req_info_dup.map(_ := RegEnable(Mux(refill_from_mq, llptw_mem.refill, ptw.io.refill.req_info), refill_valid)) 283 cache.io.refill.bits.level_dup.map(_ := RegEnable(refill_level, refill_valid)) 284 cache.io.refill.bits.levelOH(refill_level, refill_valid) 285 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source)))) 286 287 // pmp 288 pmp_check(0).req <> ptw.io.pmp.req 289 ptw.io.pmp.resp <> pmp_check(0).resp 290 pmp_check(1).req <> llptw.io.pmp.req 291 llptw.io.pmp.resp <> pmp_check(1).resp 292 293 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 294 for (i <- 0 until PtwWidth) { 295 outArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U 296 outArb(i).in(outArbCachePort).bits.entry := cache.io.resp.bits.toTlb 297 outArb(i).in(outArbCachePort).bits.pf := !cache.io.resp.bits.toTlb.v 298 outArb(i).in(outArbCachePort).bits.af := false.B 299 outArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 300 outArb(i).in(outArbFsmPort).bits := ptw.io.resp.bits.resp 301 outArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 302 outArb(i).in(outArbMqPort).bits := pte_to_ptwResp(resp_pte(llptw_out.bits.id), llptw_out.bits.req_info.vpn, llptw_out.bits.af, true) 303 } 304 305 // io.tlb.map(_.resp) <> outArb.map(_.out) 306 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 307 case (resp, out) => resp <> out 308 } 309 310 // sfence 311 when (flush) { 312 for (i <- 0 until MemReqWidth) { 313 when (waiting_resp(i)) { 314 flush_latch(i) := true.B 315 } 316 } 317 } 318 // mem -> control signal 319 // waiting_resp and sfence_latch will be reset when mem_resp_done 320 when (mem_resp_done) { 321 waiting_resp(mem.d.bits.source) := false.B 322 flush_latch(mem.d.bits.source) := false.B 323 } 324 325 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 326 sink.valid := source.valid && !block_signal 327 source.ready := sink.ready && !block_signal 328 sink.bits := source.bits 329 } 330 331 def get_part(data: Vec[UInt], index: UInt): UInt = { 332 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 333 inner_data(index) 334 } 335 336 def pte_to_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean) : PtwResp = { 337 val pte_in = pte.asTypeOf(new PteBundle()) 338 val ptw_resp = Wire(new PtwResp()) 339 ptw_resp.entry.ppn := pte_in.ppn 340 ptw_resp.entry.level.map(_ := 2.U) 341 ptw_resp.entry.perm.map(_ := pte_in.getPerm()) 342 ptw_resp.entry.tag := vpn 343 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 344 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && af 345 ptw_resp.entry.v := !ptw_resp.pf 346 ptw_resp.entry.prefetch := DontCare 347 ptw_resp.entry.asid := satp.asid 348 ptw_resp 349 } 350 351 def outReady(source: UInt, port: Int): Bool = { 352 MuxLookup(source, true.B, 353 (0 until PtwWidth).map(i => i.U -> outArb(i).in(port).ready)) 354 } 355 356 // debug info 357 for (i <- 0 until PtwWidth) { 358 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 359 } 360 XSDebug(p"[sfence] ${io.sfence}\n") 361 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 362 363 for (i <- 0 until PtwWidth) { 364 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire()) 365 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 366 } 367 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 368 for (i <- 0 until (MemReqWidth + 1)) { 369 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 370 } 371 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 372 XSPerfAccumulate("mem_count", mem.a.fire()) 373 374 // print configs 375 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 376 377 // time out assert 378 for (i <- 0 until MemReqWidth) { 379 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 380 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 381 } 382 383 384 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 385 generatePerfEvent() 386} 387 388/** BlockHelper, block missqueue, not to send too many req to cache 389 * Parameter: 390 * enable: enable BlockHelper, mq should not send too many reqs 391 * start: when miss queue out fire and need, block miss queue's out 392 * block: block miss queue's out 393 * latency: last missqueue out's cache access latency 394 */ 395class BlockHelper(latency: Int)(implicit p: Parameters) extends XSModule { 396 val io = IO(new Bundle { 397 val enable = Input(Bool()) 398 val start = Input(Bool()) 399 val block = Output(Bool()) 400 }) 401 402 val count = RegInit(0.U(log2Ceil(latency).W)) 403 val valid = RegInit(false.B) 404 val work = RegInit(true.B) 405 406 io.block := valid 407 408 when (io.start && work) { valid := true.B } 409 when (valid) { count := count + 1.U } 410 when (count === (latency.U) || io.enable) { 411 valid := false.B 412 work := io.enable 413 count := 0.U 414 } 415} 416 417class PTEHelper() extends ExtModule { 418 val clock = IO(Input(Clock())) 419 val enable = IO(Input(Bool())) 420 val satp = IO(Input(UInt(64.W))) 421 val vpn = IO(Input(UInt(64.W))) 422 val pte = IO(Output(UInt(64.W))) 423 val level = IO(Output(UInt(8.W))) 424 val pf = IO(Output(UInt(8.W))) 425} 426 427class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 428 val io = IO(new L2TLBIO) 429 430 for (i <- 0 until PtwWidth) { 431 io.tlb(i).req(0).ready := true.B 432 433 val helper = Module(new PTEHelper()) 434 helper.clock := clock 435 helper.enable := io.tlb(i).req(0).valid 436 helper.satp := io.csr.tlb.satp.ppn 437 helper.vpn := io.tlb(i).req(0).bits.vpn 438 val pte = helper.pte.asTypeOf(new PteBundle) 439 val level = helper.level 440 val pf = helper.pf 441 442 io.tlb(i).resp.valid := RegNext(io.tlb(i).req(0).valid) 443 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 444 io.tlb(i).resp.bits.entry.tag := RegNext(io.tlb(i).req(0).bits.vpn) 445 io.tlb(i).resp.bits.entry.ppn := pte.ppn 446 io.tlb(i).resp.bits.entry.perm.map(_ := pte.getPerm()) 447 io.tlb(i).resp.bits.entry.level.map(_ := level) 448 io.tlb(i).resp.bits.pf := pf 449 io.tlb(i).resp.bits.af := DontCare // TODO: implement it 450 } 451} 452 453class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 454 val useSoftPTW = coreParams.softPTW 455 val node = if (!useSoftPTW) TLIdentityNode() else null 456 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 457 if (!useSoftPTW) { 458 node := ptw.node 459 } 460 461 lazy val module = new LazyModuleImp(this) with HasPerfEvents { 462 val io = IO(new L2TLBIO) 463 val perfEvents = if (useSoftPTW) { 464 val fake_ptw = Module(new FakePTW()) 465 io <> fake_ptw.io 466 Seq() 467 } 468 else { 469 io <> ptw.module.io 470 ptw.module.getPerfEvents 471 } 472 generatePerfEvent() 473 } 474} 475