1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31import difftest._ 32 33class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 34 override def shouldBeInlined: Boolean = false 35 36 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 37 clients = Seq(TLMasterParameters.v1( 38 "ptw", 39 sourceId = IdRange(0, MemReqWidth) 40 )), 41 requestFields = Seq(ReqSourceField()) 42 ))) 43 44 lazy val module = new L2TLBImp(this) 45} 46 47class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 48 49 val (mem, edge) = outer.node.out.head 50 51 val io = IO(new L2TLBIO) 52 val difftestIO = IO(new Bundle() { 53 val ptwResp = Output(Bool()) 54 val ptwAddr = Output(UInt(64.W)) 55 val ptwData = Output(Vec(4, UInt(64.W))) 56 }) 57 58 /* Ptw processes multiple requests 59 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 60 * miss queue itlb dtlb 61 * | | | 62 * ------arbiter------ 63 * | 64 * l1 - l2 - l3 - sp 65 * | 66 * ------------------------------------------- 67 * miss | queue | hit 68 * [][][][][][] | 69 * | | 70 * state machine accessing mem | 71 * | | 72 * ---------------arbiter--------------------- 73 * | | 74 * itlb dtlb 75 */ 76 77 difftestIO <> DontCare 78 79 val sfence_tmp = DelayN(io.sfence, 1) 80 val csr_tmp = DelayN(io.csr.tlb, 1) 81 val sfence_dup = Seq.fill(9)(RegNext(sfence_tmp)) 82 val csr_dup = Seq.fill(8)(RegNext(csr_tmp)) 83 val satp = csr_dup(0).satp 84 val vsatp = csr_dup(0).vsatp 85 val hgatp = csr_dup(0).hgatp 86 val priv = csr_dup(0).priv 87 val flush = sfence_dup(0).valid || satp.changed || vsatp.changed || hgatp.changed 88 89 val pmp = Module(new PMP()) 90 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 91 pmp.io.distribute_csr := io.csr.distribute_csr 92 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 93 94 val missQueue = Module(new L2TlbMissQueue) 95 val cache = Module(new PtwCache) 96 val ptw = Module(new PTW) 97 val hptw = Module(new HPTW) 98 val llptw = Module(new LLPTW) 99 val blockmq = Module(new BlockHelper(3)) 100 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 101 val arb2 = Module(new Arbiter(new Bundle { 102 val vpn = UInt(vpnLen.W) 103 val s2xlate = UInt(2.W) 104 val source = UInt(bSourceWidth.W) 105 }, if (l2tlbParams.enablePrefetch) 4 else 3 + (if(HasHExtension) 1 else 0))) 106 val hptw_req_arb = Module(new Arbiter(new Bundle { 107 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 108 val gvpn = UInt(vpnLen.W) 109 }, 2)) 110 val hptw_resp_arb = Module(new Arbiter(new Bundle { 111 val resp = new HptwResp() 112 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 113 }, 2)) 114 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 115 val s2xlate = UInt(2.W) 116 val s1Resp = new PtwSectorResp () 117 val s2Resp = new HptwResp() 118 }, 1)).io) 119 val mergeArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 120 val s2xlate = UInt(2.W) 121 val s1Resp = new PtwMergeResp() 122 val s2Resp = new HptwResp() 123 }, 3)).io) 124 val outArbCachePort = 0 125 val outArbFsmPort = 1 126 val outArbMqPort = 2 127 128 // hptw arb input port 129 val InHptwArbPTWPort = 0 130 val InHptwArbLLPTWPort = 1 131 hptw_req_arb.io.in(InHptwArbPTWPort).valid := ptw.io.hptw.req.valid 132 hptw_req_arb.io.in(InHptwArbPTWPort).bits.gvpn := ptw.io.hptw.req.bits.gvpn 133 hptw_req_arb.io.in(InHptwArbPTWPort).bits.id := ptw.io.hptw.req.bits.id 134 ptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbPTWPort).ready 135 136 hptw_req_arb.io.in(InHptwArbLLPTWPort).valid := llptw.io.hptw.req.valid 137 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.gvpn := llptw.io.hptw.req.bits.gvpn 138 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.id := llptw.io.hptw.req.bits.id 139 llptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbLLPTWPort).ready 140 141 val hptw_id = RegInit(0.U(log2Up(l2tlbParams.llptwsize).W)) 142 when(hptw_req_arb.io.out.valid) { 143 hptw_id := hptw_req_arb.io.out.bits.id 144 } 145 // arb2 input port 146 val InArbPTWPort = 0 147 val InArbMissQueuePort = 1 148 val InArbTlbPort = 2 149 val InArbPrefetchPort = 3 150 val InArbHPTWPort = 4 151 // NOTE: when cache out but miss and ptw doesnt accept, 152 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 153 arb1.io.out.ready := arb2.io.in(InArbTlbPort).ready 154 155 arb2.io.in(InArbPTWPort).valid := ptw.io.llptw.valid 156 arb2.io.in(InArbPTWPort).bits.vpn := ptw.io.llptw.bits.req_info.vpn 157 arb2.io.in(InArbPTWPort).bits.s2xlate := ptw.io.llptw.bits.req_info.s2xlate 158 arb2.io.in(InArbPTWPort).bits.source := ptw.io.llptw.bits.req_info.source 159 ptw.io.llptw.ready := arb2.io.in(InArbPTWPort).ready 160 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 161 162 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 163 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 164 arb2.io.in(InArbTlbPort).bits.s2xlate := arb1.io.out.bits.s2xlate 165 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 166 167 arb2.io.in(InArbHPTWPort).valid := hptw_req_arb.io.out.valid 168 arb2.io.in(InArbHPTWPort).bits.vpn := hptw_req_arb.io.out.bits.gvpn 169 arb2.io.in(InArbHPTWPort).bits.s2xlate := onlyStage2 170 arb2.io.in(InArbHPTWPort).bits.source := DontCare 171 if (l2tlbParams.enablePrefetch) { 172 val prefetch = Module(new L2TlbPrefetch()) 173 val recv = cache.io.resp 174 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 175 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 176 prefetch.io.in.valid := recv.fire && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 177 recv.bits.prefetch) && recv.bits.isFirst 178 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 179 prefetch.io.sfence := sfence_dup(0) 180 prefetch.io.csr := csr_dup(0) 181 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 182 183 val isWriteL2TlbPrefetchTable = WireInit(Constantin.createRecord("isWriteL2TlbPrefetchTable" + p(XSCoreParamsKey).HartId.toString)) 184 val L2TlbPrefetchTable = ChiselDB.createTable("L2TlbPrefetch_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbPrefetchDB) 185 val L2TlbPrefetchDB = Wire(new L2TlbPrefetchDB) 186 L2TlbPrefetchDB.vpn := prefetch.io.out.bits.vpn 187 L2TlbPrefetchTable.log(L2TlbPrefetchDB, isWriteL2TlbPrefetchTable.orR && prefetch.io.out.fire, "L2TlbPrefetch", clock, reset) 188 } 189 arb2.io.out.ready := cache.io.req.ready 190 191 192 val mq_arb = Module(new Arbiter(new L2TlbInnerBundle, 2)) 193 mq_arb.io.in(0).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 194 (!cache.io.resp.bits.toFsm.l2Hit || cache.io.resp.bits.bypassed) && 195 !from_pre(cache.io.resp.bits.req_info.source) && 196 (cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst || !ptw.io.req.ready) 197 mq_arb.io.in(0).bits := cache.io.resp.bits.req_info 198 mq_arb.io.in(1) <> llptw.io.cache 199 missQueue.io.in <> mq_arb.io.out 200 missQueue.io.sfence := sfence_dup(6) 201 missQueue.io.csr := csr_dup(5) 202 203 blockmq.io.start := missQueue.io.out.fire 204 blockmq.io.enable := ptw.io.req.fire 205 206 llptw.io.in.valid := cache.io.resp.valid && 207 !cache.io.resp.bits.hit && 208 cache.io.resp.bits.toFsm.l2Hit && 209 !cache.io.resp.bits.bypassed && 210 !cache.io.resp.bits.isHptw 211 llptw.io.in.bits.req_info := cache.io.resp.bits.req_info 212 llptw.io.in.bits.ppn := cache.io.resp.bits.toFsm.ppn 213 llptw.io.sfence := sfence_dup(1) 214 llptw.io.csr := csr_dup(1) 215 216 cache.io.req.valid := arb2.io.out.valid 217 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 218 cache.io.req.bits.req_info.s2xlate := arb2.io.out.bits.s2xlate 219 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 220 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 221 cache.io.req.bits.isHptw := arb2.io.chosen === InArbHPTWPort.U 222 cache.io.req.bits.hptwId := hptw_id 223 cache.io.req.bits.bypassed.map(_ := false.B) 224 cache.io.sfence := sfence_dup(2) 225 cache.io.csr := csr_dup(2) 226 cache.io.sfence_dup.zip(sfence_dup.drop(2).take(4)).map(s => s._1 := s._2) 227 cache.io.csr_dup.zip(csr_dup.drop(2).take(3)).map(c => c._1 := c._2) 228 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 229 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 230 Mux(cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed, llptw.io.in.ready, 231 Mux(cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst, mq_arb.io.in(0).ready, mq_arb.io.in(0).ready || ptw.io.req.ready))) 232 233 // NOTE: missQueue req has higher priority 234 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit && 235 !cache.io.resp.bits.bypassed && 236 !cache.io.resp.bits.isFirst && 237 !cache.io.resp.bits.isHptw 238 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 239 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 240 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 241 ptw.io.sfence := sfence_dup(7) 242 ptw.io.csr := csr_dup(6) 243 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 244 245 hptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.bypassed & cache.io.resp.bits.isHptw 246 hptw.io.req.bits.gvpn := cache.io.resp.bits.req_info.vpn 247 hptw.io.req.bits.id := cache.io.resp.bits.toHptw.id 248 hptw.io.req.bits.l1Hit := cache.io.resp.bits.toHptw.l1Hit 249 hptw.io.req.bits.l2Hit := cache.io.resp.bits.toHptw.l2Hit 250 hptw.io.sfence := sfence_dup(8) 251 hptw.io.csr := csr_dup(7) 252 // mem req 253 def blockBytes_align(addr: UInt) = { 254 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 255 } 256 def addr_low_from_vpn(vpn: UInt) = { 257 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 258 } 259 def addr_low_from_paddr(paddr: UInt) = { 260 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 261 } 262 def from_llptw(id: UInt) = { 263 id < l2tlbParams.llptwsize.U 264 } 265 def from_ptw(id: UInt) = { 266 id === l2tlbParams.llptwsize.U 267 } 268 def from_hptw(id: UInt) = { 269 id === l2tlbParams.llptwsize.U + 1.U 270 } 271 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 272 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 273 for (i <- waiting_resp.indices) { 274 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 275 } 276 277 val llptw_out = llptw.io.out 278 val llptw_mem = llptw.io.mem 279 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 280 ptw.io.mem.mask := waiting_resp.apply(l2tlbParams.llptwsize) 281 hptw.io.mem.mask := waiting_resp.apply(l2tlbParams.llptwsize + 1) 282 283 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 3)) 284 mem_arb.io.in(0) <> ptw.io.mem.req 285 mem_arb.io.in(1) <> llptw_mem.req 286 mem_arb.io.in(2) <> hptw.io.mem.req 287 mem_arb.io.out.ready := mem.a.ready && !flush 288 289 // assert, should not send mem access at same addr for twice. 290 val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info_dup(0).vpn, cache.io.refill.valid) 291 val last_resp_level = RegEnable(cache.io.refill.bits.level_dup(0), cache.io.refill.valid) 292 val last_resp_v = RegInit(false.B) 293 val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR || cache.io.refill.bits.sel_pte_dup(0).asTypeOf(new PteBundle).isAf() 294 when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 295 when (flush) { last_resp_v := false.B } 296 XSError(last_resp_v && cache.io.refill.valid && 297 (cache.io.refill.bits.req_info_dup(0).vpn === last_resp_vpn) && 298 (cache.io.refill.bits.level_dup(0) === last_resp_level), 299 "l2tlb should not access mem at same addr for twice") 300 // ATTENTION: this may wrongly assert when: a ptes is l2, last part is valid, 301 // but the current part is invalid, so one more mem access happened 302 // If this happened, remove the assert. 303 304 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 305 306 when (llptw.io.in.fire) { 307 // when enq miss queue, set the req_addr_low to receive the mem resp data part 308 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 309 } 310 when (mem_arb.io.out.fire) { 311 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 312 waiting_resp(mem_arb.io.out.bits.id) := true.B 313 } 314 // mem read 315 val memRead = edge.Get( 316 fromSource = mem_arb.io.out.bits.id, 317 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 318 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 319 lgSize = log2Up(l2tlbParams.blockBytes).U 320 )._2 321 mem.a.bits := memRead 322 mem.a.valid := mem_arb.io.out.valid && !flush 323 mem.a.bits.user.lift(ReqSourceKey).foreach(_ := MemReqSource.PTW.id.U) 324 mem.d.ready := true.B 325 // mem -> data buffer 326 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 327 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire) 328 val mem_resp_done = refill_helper._3 329 val mem_resp_from_llptw = from_llptw(mem.d.bits.source) 330 val mem_resp_from_ptw = from_ptw(mem.d.bits.source) 331 val mem_resp_from_hptw = from_hptw(mem.d.bits.source) 332 when (mem.d.valid) { 333 assert(mem.d.bits.source < MemReqWidth.U) 334 refill_data(refill_helper._4) := mem.d.bits.data 335 } 336 // refill_data_tmp is the wire fork of refill_data, but one cycle earlier 337 val refill_data_tmp = WireInit(refill_data) 338 refill_data_tmp(refill_helper._4) := mem.d.bits.data 339 340 // save only one pte for each id 341 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 342 val resp_pte = VecInit((0 until MemReqWidth).map(i => 343 if (i == l2tlbParams.llptwsize + 1) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && mem_resp_from_hptw) } 344 else if (i == l2tlbParams.llptwsize) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && mem_resp_from_ptw) } 345 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 346 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 347 )) 348 349 // save eight ptes for each id when sector tlb 350 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 351 val resp_pte_sector = VecInit((0 until MemReqWidth).map(i => 352 if (i == l2tlbParams.llptwsize + 1) {RegEnable(refill_data_tmp, mem_resp_done && mem_resp_from_hptw) } 353 else if (i == l2tlbParams.llptwsize) {RegEnable(refill_data_tmp, mem_resp_done && mem_resp_from_ptw) } 354 else { DataHoldBypass(refill_data, llptw_mem.buffer_it(i)) } 355 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 356 )) 357 358 // mem -> llptw 359 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_llptw 360 llptw_mem.resp.bits.id := DataHoldBypass(mem.d.bits.source, mem.d.valid) 361 // mem -> ptw 362 ptw.io.mem.req.ready := mem.a.ready 363 ptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_ptw 364 ptw.io.mem.resp.bits := resp_pte.apply(l2tlbParams.llptwsize) 365 // mem -> hptw 366 hptw.io.mem.req.ready := mem.a.ready 367 hptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_hptw 368 hptw.io.mem.resp.bits := resp_pte.apply(l2tlbParams.llptwsize + 1) 369 // mem -> cache 370 val refill_from_llptw = mem_resp_from_llptw 371 val refill_from_ptw = mem_resp_from_ptw 372 val refill_from_hptw = mem_resp_from_hptw 373 val refill_level = Mux(refill_from_llptw, 2.U, Mux(refill_from_ptw, RegEnable(ptw.io.refill.level, init = 0.U, ptw.io.mem.req.fire()), RegEnable(hptw.io.refill.level, init = 0.U, hptw.io.mem.req.fire()))) 374 val refill_valid = mem_resp_done && !flush && !flush_latch(mem.d.bits.source) 375 376 cache.io.refill.valid := RegNext(refill_valid, false.B) 377 cache.io.refill.bits.ptes := refill_data.asUInt 378 cache.io.refill.bits.req_info_dup.map(_ := RegEnable(Mux(refill_from_llptw, llptw_mem.refill, Mux(refill_from_ptw, ptw.io.refill.req_info, hptw.io.refill.req_info)), refill_valid)) 379 cache.io.refill.bits.level_dup.map(_ := RegEnable(refill_level, refill_valid)) 380 cache.io.refill.bits.levelOH(refill_level, refill_valid) 381 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source)))) 382 383 if (env.EnableDifftest) { 384 val difftest_ptw_addr = RegInit(VecInit(Seq.fill(MemReqWidth)(0.U(PAddrBits.W)))) 385 when (mem.a.valid) { 386 difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address 387 } 388 389 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) 390 difftest.coreid := io.hartId 391 difftest.index := 2.U 392 difftest.valid := cache.io.refill.valid 393 difftest.addr := difftest_ptw_addr(RegNext(mem.d.bits.source)) 394 difftest.data := refill_data.asTypeOf(difftest.data) 395 difftest.idtfr := DontCare 396 } 397 398 if (env.EnableDifftest) { 399 for (i <- 0 until PtwWidth) { 400 val difftest = DifftestModule(new DiffL2TLBEvent) 401 difftest.coreid := io.hartId 402 difftest.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.s1.af && !io.tlb(i).resp.bits.s2.gaf 403 difftest.index := i.U 404 difftest.satp := io.csr.tlb.satp.ppn 405 difftest.vpn := Cat(io.tlb(i).resp.bits.entry.tag, 0.U(sectortlbwidth.W)) 406 for (j <- 0 until tlbcontiguous) { 407 difftest.ppn(j) := Cat(io.tlb(i).resp.bits.entry.ppn, io.tlb(i).resp.bits.ppn_low(j)) 408 difftest.valididx(j) := io.tlb(i).resp.bits.valididx(j) 409 difftest.io.pteidx(j) := io.tlb(i).resp.bits.s1.pteidx(j) 410 } 411 difftest.perm := io.tlb(i).resp.bits.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 412 difftest.level := io.tlb(i).resp.bits.entry.level.getOrElse(0.U.asUInt) 413 difftest.pf := io.tlb(i).resp.bits.pf 414 } 415 } 416 417 // pmp 418 pmp_check(0).req <> ptw.io.pmp.req 419 ptw.io.pmp.resp <> pmp_check(0).resp 420 pmp_check(1).req <> llptw.io.pmp.req 421 llptw.io.pmp.resp <> pmp_check(1).resp 422 423 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 424 425 // hptw and page cache -> ptw and llptw 426 val HptwRespArbCachePort = 0 427 val HptwRespArbHptw = 0 428 hptw_resp_arb.io.in(HptwRespArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.isHptw 429 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.id := cache.io.resp.bits.toHptw.id 430 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.resp := cache.io.resp.bits.toHptw.resp 431 hptw_resp_arb.io.in(HptwRespArbHptw).valid := hptw.io.resp.valid 432 hptw_resp_arb.io.in(HptwRespArbHptw).bits.id := hptw.io.resp.bits.id 433 hptw_resp_arb.io.in(HptwRespArbHptw).bits.resp := hptw.io.resp.bits.resp 434 435 ptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id === FsmReqID.U 436 ptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 437 llptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id =/= FsmReqID.U 438 llptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 439 440 // Timing: Maybe need to do some optimization or even add one more cycle 441 for (i <- 0 until PtwWidth) { 442 mergeArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U 443 mergeArb(i).in(outArbCachePort).bits.s2xlate := cache.io.resp.bits.req_info.s2xlate 444 mergeArb(i).in(outArbCachePort).bits.s1Resp := cache.io.resp.bits.toTlb 445 mergeArb(i).in(outArbCachePort).bits.s2Resp := cache.io.resp.bits.toHptw.resp 446 mergeArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 447 mergeArb(i).in(outArbFsmPort).bits.s2xlate := ptw.io.resp.bits.s2xlate 448 mergeArb(i).in(outArbFsmPort).bits.s1Resp := ptw.io.resp.bits.resp 449 mergeArb(i).in(outArbFsmPort).bits.s2Resp := ptw.io.resp.bits.h_resp 450 mergeArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 451 mergeArb(i).in(outArbMqPort).bits.s2xlate := llptw_out.bits.req_info.s2xlate 452 mergeArb(i).in(outArbMqPort).bits.s1Resp := contiguous_pte_to_merge_ptwResp(resp_pte_sector(llptw_out.bits.id).asUInt, llptw_out.bits.req_info.vpn, llptw_out.bits.af, true) 453 mergeArb(i).in(outArbMqPort).bits.s2Resp := llptw_out.bits.h_resp 454 mergeArb(i).out.ready := outArb(i).in(0).ready 455 } 456 457 for (i <- 0 until PtwWidth) { 458 outArb(i).in(0).valid := mergeArb(i).out.valid 459 outArb(i).in(0).bits.s1Resp := merge_ptwResp_to_sector_ptwResp(mergeArb(i).out.bits.s1Resp) 460 outArb(i).in(0).bits.s2Resp := mergeArb(i).out.bits.s2Resp 461 } 462 463 // io.tlb.map(_.resp) <> outArb.map(_.out) 464 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 465 case (resp, out) => resp <> out 466 } 467 468 // sfence 469 when (flush) { 470 for (i <- 0 until MemReqWidth) { 471 when (waiting_resp(i)) { 472 flush_latch(i) := true.B 473 } 474 } 475 } 476 // mem -> control signal 477 // waiting_resp and sfence_latch will be reset when mem_resp_done 478 when (mem_resp_done) { 479 waiting_resp(mem.d.bits.source) := false.B 480 flush_latch(mem.d.bits.source) := false.B 481 } 482 483 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 484 sink.valid := source.valid && !block_signal 485 source.ready := sink.ready && !block_signal 486 sink.bits := source.bits 487 } 488 489 def get_part(data: Vec[UInt], index: UInt): UInt = { 490 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 491 inner_data(index) 492 } 493 494 // not_super means that this is a normal page 495 // valididx(i) will be all true when super page to be convenient for l1 tlb matching 496 def contiguous_pte_to_merge_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean, not_super: Boolean = true) : PtwMergeResp = { 497 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 498 val ptw_merge_resp = Wire(new PtwMergeResp()) 499 for (i <- 0 until tlbcontiguous) { 500 val pte_in = pte(64 * i + 63, 64 * i).asTypeOf(new PteBundle()) 501 val ptw_resp = Wire(new PtwMergeEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true)) 502 ptw_resp.ppn := pte_in.ppn(ppnLen - 1, sectortlbwidth) 503 ptw_resp.ppn_low := pte_in.ppn(sectortlbwidth - 1, 0) 504 ptw_resp.level.map(_ := 2.U) 505 ptw_resp.perm.map(_ := pte_in.getPerm()) 506 ptw_resp.tag := vpn(vpnLen - 1, sectortlbwidth) 507 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 508 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && (af || pte_in.isAf()) 509 ptw_resp.v := !ptw_resp.pf 510 ptw_resp.prefetch := DontCare 511 ptw_resp.asid := satp.asid 512 ptw_merge_resp.entry(i) := ptw_resp 513 } 514 ptw_merge_resp.pteidx := UIntToOH(vpn(sectortlbwidth - 1, 0)).asBools 515 ptw_merge_resp.not_super := not_super.B 516 ptw_merge_resp 517 } 518 519 def merge_ptwResp_to_sector_ptwResp(pte: PtwMergeResp) : PtwSectorResp = { 520 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 521 val ptw_sector_resp = Wire(new PtwSectorResp) 522 ptw_sector_resp.entry.tag := pte.entry(OHToUInt(pte.pteidx)).tag 523 ptw_sector_resp.entry.asid := pte.entry(OHToUInt(pte.pteidx)).asid 524 ptw_sector_resp.entry.ppn := pte.entry(OHToUInt(pte.pteidx)).ppn 525 ptw_sector_resp.entry.perm.map(_ := pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle))) 526 ptw_sector_resp.entry.level.map(_ := pte.entry(OHToUInt(pte.pteidx)).level.getOrElse(0.U(2.W))) 527 ptw_sector_resp.entry.prefetch := pte.entry(OHToUInt(pte.pteidx)).prefetch 528 ptw_sector_resp.entry.v := pte.entry(OHToUInt(pte.pteidx)).v 529 ptw_sector_resp.af := pte.entry(OHToUInt(pte.pteidx)).af 530 ptw_sector_resp.pf := pte.entry(OHToUInt(pte.pteidx)).pf 531 ptw_sector_resp.addr_low := OHToUInt(pte.pteidx) 532 ptw_sector_resp.pteidx := pte.pteidx 533 for (i <- 0 until tlbcontiguous) { 534 val ppn_equal = pte.entry(i).ppn === pte.entry(OHToUInt(pte.pteidx)).ppn 535 val perm_equal = pte.entry(i).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt === pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 536 val v_equal = pte.entry(i).v === pte.entry(OHToUInt(pte.pteidx)).v 537 val af_equal = pte.entry(i).af === pte.entry(OHToUInt(pte.pteidx)).af 538 val pf_equal = pte.entry(i).pf === pte.entry(OHToUInt(pte.pteidx)).pf 539 ptw_sector_resp.valididx(i) := (ppn_equal && perm_equal && v_equal && af_equal && pf_equal) || !pte.not_super 540 ptw_sector_resp.ppn_low(i) := pte.entry(i).ppn_low 541 } 542 ptw_sector_resp.valididx(OHToUInt(pte.pteidx)) := true.B 543 ptw_sector_resp 544 } 545 546 def outReady(source: UInt, port: Int): Bool = { 547 MuxLookup(source, true.B)((0 until PtwWidth).map(i => i.U -> mergeArb(i).in(port).ready)) 548 } 549 550 // debug info 551 for (i <- 0 until PtwWidth) { 552 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 553 } 554 XSDebug(p"[sfence] ${io.sfence}\n") 555 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 556 557 for (i <- 0 until PtwWidth) { 558 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire) 559 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 560 } 561 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 562 for (i <- 0 until (MemReqWidth + 1)) { 563 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 564 } 565 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 566 XSPerfAccumulate("mem_count", mem.a.fire) 567 for (i <- 0 until PtwWidth) { 568 XSPerfAccumulate(s"llptw_ppn_af${i}", mergeArb(i).in(outArbMqPort).valid && mergeArb(i).in(outArbMqPort).bits.s1Resp.entry(OHToUInt(mergeArb(i).in(outArbMqPort).bits.s1Resp.pteidx)).af && !llptw_out.bits.af) 569 XSPerfAccumulate(s"access_fault${i}", io.tlb(i).resp.fire && io.tlb(i).resp.bits.s1.af) 570 } 571 572 // print configs 573 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 574 575 // time out assert 576 for (i <- 0 until MemReqWidth) { 577 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 578 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 579 } 580 581 582 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 583 generatePerfEvent() 584 585 val isWriteL1TlbTable = WireInit(Constantin.createRecord("isWriteL1TlbTable" + p(XSCoreParamsKey).HartId.toString)) 586 val L1TlbTable = ChiselDB.createTable("L1Tlb_hart" + p(XSCoreParamsKey).HartId.toString, new L1TlbDB) 587 val ITlbReqDB, DTlbReqDB, ITlbRespDB, DTlbRespDB = Wire(new L1TlbDB) 588 ITlbReqDB.vpn := io.tlb(0).req(0).bits.vpn 589 DTlbReqDB.vpn := io.tlb(1).req(0).bits.vpn 590 ITlbRespDB.vpn := io.tlb(0).resp.bits.s1.entry.tag 591 DTlbRespDB.vpn := io.tlb(1).resp.bits.s1.entry.tag 592 L1TlbTable.log(ITlbReqDB, isWriteL1TlbTable.orR && io.tlb(0).req(0).fire, "ITlbReq", clock, reset) 593 L1TlbTable.log(DTlbReqDB, isWriteL1TlbTable.orR && io.tlb(1).req(0).fire, "DTlbReq", clock, reset) 594 L1TlbTable.log(ITlbRespDB, isWriteL1TlbTable.orR && io.tlb(0).resp.fire, "ITlbResp", clock, reset) 595 L1TlbTable.log(DTlbRespDB, isWriteL1TlbTable.orR && io.tlb(1).resp.fire, "DTlbResp", clock, reset) 596 597 val isWritePageCacheTable = WireInit(Constantin.createRecord("isWritePageCacheTable" + p(XSCoreParamsKey).HartId.toString)) 598 val PageCacheTable = ChiselDB.createTable("PageCache_hart" + p(XSCoreParamsKey).HartId.toString, new PageCacheDB) 599 val PageCacheDB = Wire(new PageCacheDB) 600 PageCacheDB.vpn := Cat(cache.io.resp.bits.toTlb.entry(0).tag, OHToUInt(cache.io.resp.bits.toTlb.pteidx)) 601 PageCacheDB.source := cache.io.resp.bits.req_info.source 602 PageCacheDB.bypassed := cache.io.resp.bits.bypassed 603 PageCacheDB.is_first := cache.io.resp.bits.isFirst 604 PageCacheDB.prefetched := cache.io.resp.bits.toTlb.entry(0).prefetch 605 PageCacheDB.prefetch := cache.io.resp.bits.prefetch 606 PageCacheDB.l2Hit := cache.io.resp.bits.toFsm.l2Hit 607 PageCacheDB.l1Hit := cache.io.resp.bits.toFsm.l1Hit 608 PageCacheDB.hit := cache.io.resp.bits.hit 609 PageCacheTable.log(PageCacheDB, isWritePageCacheTable.orR && cache.io.resp.fire, "PageCache", clock, reset) 610 611 val isWritePTWTable = WireInit(Constantin.createRecord("isWritePTWTable" + p(XSCoreParamsKey).HartId.toString)) 612 val PTWTable = ChiselDB.createTable("PTW_hart" + p(XSCoreParamsKey).HartId.toString, new PTWDB) 613 val PTWReqDB, PTWRespDB, LLPTWReqDB, LLPTWRespDB = Wire(new PTWDB) 614 PTWReqDB.vpn := ptw.io.req.bits.req_info.vpn 615 PTWReqDB.source := ptw.io.req.bits.req_info.source 616 PTWRespDB.vpn := ptw.io.refill.req_info.vpn 617 PTWRespDB.source := ptw.io.refill.req_info.source 618 LLPTWReqDB.vpn := llptw.io.in.bits.req_info.vpn 619 LLPTWReqDB.source := llptw.io.in.bits.req_info.source 620 LLPTWRespDB.vpn := llptw.io.mem.refill.vpn 621 LLPTWRespDB.source := llptw.io.mem.refill.source 622 PTWTable.log(PTWReqDB, isWritePTWTable.orR && ptw.io.req.fire, "PTWReq", clock, reset) 623 PTWTable.log(PTWRespDB, isWritePTWTable.orR && ptw.io.mem.resp.fire, "PTWResp", clock, reset) 624 PTWTable.log(LLPTWReqDB, isWritePTWTable.orR && llptw.io.in.fire, "LLPTWReq", clock, reset) 625 PTWTable.log(LLPTWRespDB, isWritePTWTable.orR && llptw.io.mem.resp.fire, "LLPTWResp", clock, reset) 626 627 val isWriteL2TlbMissQueueTable = WireInit(Constantin.createRecord("isWriteL2TlbMissQueueTable" + p(XSCoreParamsKey).HartId.toString)) 628 val L2TlbMissQueueTable = ChiselDB.createTable("L2TlbMissQueue_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbMissQueueDB) 629 val L2TlbMissQueueInDB, L2TlbMissQueueOutDB = Wire(new L2TlbMissQueueDB) 630 L2TlbMissQueueInDB.vpn := missQueue.io.in.bits.vpn 631 L2TlbMissQueueOutDB.vpn := missQueue.io.out.bits.vpn 632 L2TlbMissQueueTable.log(L2TlbMissQueueInDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.in.fire, "L2TlbMissQueueIn", clock, reset) 633 L2TlbMissQueueTable.log(L2TlbMissQueueOutDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.out.fire, "L2TlbMissQueueOut", clock, reset) 634} 635 636/** BlockHelper, block missqueue, not to send too many req to cache 637 * Parameter: 638 * enable: enable BlockHelper, mq should not send too many reqs 639 * start: when miss queue out fire and need, block miss queue's out 640 * block: block miss queue's out 641 * latency: last missqueue out's cache access latency 642 */ 643class BlockHelper(latency: Int)(implicit p: Parameters) extends XSModule { 644 val io = IO(new Bundle { 645 val enable = Input(Bool()) 646 val start = Input(Bool()) 647 val block = Output(Bool()) 648 }) 649 650 val count = RegInit(0.U(log2Ceil(latency).W)) 651 val valid = RegInit(false.B) 652 val work = RegInit(true.B) 653 654 io.block := valid 655 656 when (io.start && work) { valid := true.B } 657 when (valid) { count := count + 1.U } 658 when (count === (latency.U) || io.enable) { 659 valid := false.B 660 work := io.enable 661 count := 0.U 662 } 663} 664 665class PTEHelper() extends ExtModule { 666 val clock = IO(Input(Clock())) 667 val enable = IO(Input(Bool())) 668 val satp = IO(Input(UInt(64.W))) 669 val vpn = IO(Input(UInt(64.W))) 670 val pte = IO(Output(UInt(64.W))) 671 val level = IO(Output(UInt(8.W))) 672 val pf = IO(Output(UInt(8.W))) 673} 674 675class PTWDelayN[T <: Data](gen: T, n: Int, flush: Bool) extends Module { 676 val io = IO(new Bundle() { 677 val in = Input(gen) 678 val out = Output(gen) 679 val ptwflush = Input(flush.cloneType) 680 }) 681 val out = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 682 val t = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 683 out(0) := io.in 684 if (n == 1) { 685 io.out := out(0) 686 } else { 687 when (io.ptwflush) { 688 for (i <- 0 until n) { 689 t(i) := 0.U.asTypeOf(gen) 690 out(i) := 0.U.asTypeOf(gen) 691 } 692 io.out := 0.U.asTypeOf(gen) 693 } .otherwise { 694 for (i <- 1 until n) { 695 t(i-1) := out(i-1) 696 out(i) := t(i-1) 697 } 698 io.out := out(n-1) 699 } 700 } 701} 702 703object PTWDelayN { 704 def apply[T <: Data](in: T, n: Int, flush: Bool): T = { 705 val delay = Module(new PTWDelayN(in.cloneType, n, flush)) 706 delay.io.in := in 707 delay.io.ptwflush := flush 708 delay.io.out 709 } 710} 711 712class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 713 val io = IO(new L2TLBIO) 714 val flush = VecInit(Seq.fill(PtwWidth)(false.B)) 715 flush(0) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, itlbParams.fenceDelay) 716 flush(1) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, ldtlbParams.fenceDelay) 717 for (i <- 0 until PtwWidth) { 718 val helper = Module(new PTEHelper()) 719 helper.clock := clock 720 helper.satp := io.csr.tlb.satp.ppn 721 722 if (coreParams.softPTWDelay == 1) { 723 helper.enable := io.tlb(i).req(0).fire 724 helper.vpn := io.tlb(i).req(0).bits.vpn 725 } else { 726 helper.enable := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay - 1, flush(i)) 727 helper.vpn := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay - 1, flush(i)) 728 } 729 730 val pte = helper.pte.asTypeOf(new PteBundle) 731 val level = helper.level 732 val pf = helper.pf 733 val empty = RegInit(true.B) 734 when (io.tlb(i).req(0).fire) { 735 empty := false.B 736 } .elsewhen (io.tlb(i).resp.fire || flush(i)) { 737 empty := true.B 738 } 739 740 io.tlb(i).req(0).ready := empty || io.tlb(i).resp.fire 741 io.tlb(i).resp.valid := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay, flush(i)) 742 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 743 io.tlb(i).resp.bits.s1.entry.tag := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay, flush(i)) 744 io.tlb(i).resp.bits.s1.entry.ppn := pte.ppn 745 io.tlb(i).resp.bits.s1.entry.perm.map(_ := pte.getPerm()) 746 io.tlb(i).resp.bits.s1.entry.level.map(_ := level) 747 io.tlb(i).resp.bits.s1.pf := pf 748 io.tlb(i).resp.bits.s1.af := DontCare // TODO: implement it 749 io.tlb(i).resp.bits.s1.entry.v := !pf 750 io.tlb(i).resp.bits.s1.entry.prefetch := DontCare 751 io.tlb(i).resp.bits.s1.entry.asid := io.csr.tlb.satp.asid 752 } 753} 754 755class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 756 override def shouldBeInlined: Boolean = false 757 val useSoftPTW = coreParams.softPTW 758 val node = if (!useSoftPTW) TLIdentityNode() else null 759 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 760 if (!useSoftPTW) { 761 node := ptw.node 762 } 763 764 class L2TLBWrapperImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) with HasPerfEvents { 765 val io = IO(new L2TLBIO) 766 val perfEvents = if (useSoftPTW) { 767 val fake_ptw = Module(new FakePTW()) 768 io <> fake_ptw.io 769 Seq() 770 } 771 else { 772 io <> ptw.module.io 773 ptw.module.getPerfEvents 774 } 775 generatePerfEvent() 776 } 777 778 lazy val module = new L2TLBWrapperImp(this) 779} 780