1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31import difftest._ 32 33class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 34 override def shouldBeInlined: Boolean = false 35 36 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 37 clients = Seq(TLMasterParameters.v1( 38 "ptw", 39 sourceId = IdRange(0, MemReqWidth) 40 )), 41 requestFields = Seq(ReqSourceField()) 42 ))) 43 44 lazy val module = new L2TLBImp(this) 45} 46 47class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 48 49 val (mem, edge) = outer.node.out.head 50 51 val io = IO(new L2TLBIO) 52 val difftestIO = IO(new Bundle() { 53 val ptwResp = Output(Bool()) 54 val ptwAddr = Output(UInt(64.W)) 55 val ptwData = Output(Vec(4, UInt(64.W))) 56 }) 57 58 /* Ptw processes multiple requests 59 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 60 * miss queue itlb dtlb 61 * | | | 62 * ------arbiter------ 63 * | 64 * l1 - l2 - l3 - sp 65 * | 66 * ------------------------------------------- 67 * miss | queue | hit 68 * [][][][][][] | 69 * | | 70 * state machine accessing mem | 71 * | | 72 * ---------------arbiter--------------------- 73 * | | 74 * itlb dtlb 75 */ 76 77 difftestIO <> DontCare 78 79 val sfence_tmp = DelayN(io.sfence, 1) 80 val csr_tmp = DelayN(io.csr.tlb, 1) 81 val sfence_dup = Seq.fill(9)(RegNext(sfence_tmp)) 82 val csr_dup = Seq.fill(8)(RegNext(csr_tmp)) 83 val satp = csr_dup(0).satp 84 val vsatp = csr_dup(0).vsatp 85 val hgatp = csr_dup(0).hgatp 86 val priv = csr_dup(0).priv 87 val flush = sfence_dup(0).valid || satp.changed || vsatp.changed || hgatp.changed 88 89 val pmp = Module(new PMP()) 90 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 91 pmp.io.distribute_csr := io.csr.distribute_csr 92 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 93 94 val missQueue = Module(new L2TlbMissQueue) 95 val cache = Module(new PtwCache) 96 val ptw = Module(new PTW) 97 val hptw = Module(new HPTW) 98 val llptw = Module(new LLPTW) 99 val blockmq = Module(new BlockHelper(3)) 100 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 101 val arb2 = Module(new Arbiter(new Bundle { 102 val vpn = UInt(vpnLen.W) 103 val gvpn = UInt(gvpnLen.W) 104 val s2xlate = UInt(2.W) 105 val source = UInt(bSourceWidth.W) 106 }, if (l2tlbParams.enablePrefetch) 4 else 3 + if(l2tlbParams.HasHExtension) 1 else 0)) 107 val hptw_req_arb = Module(new Arbiter(new Bundle { 108 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 109 val gvpn = UInt(gvpnLen.W) 110 }, 2)) 111 val hptw_resp_arb = Module(new Arbiter(new Bundle { 112 val resp = new HptwResp() 113 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 114 }, 2)) 115 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 116 val s2xlate = UInt(2.W) 117 val s1Resp = new PtwSectorResp () 118 val s2Resp = new HptwResp() 119 }, 1)).io) 120 val mergeArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 121 val s2xlate = UInt(2.W) 122 val s1Resp = new PtwMergeResp() 123 val s2Resp = new HptwResp() 124 }, 3)).io) 125 val outArbCachePort = 0 126 val outArbFsmPort = 1 127 val outArbMqPort = 2 128 129 // hptw arb input port 130 val InHptwArbPTWPort = 0 131 val InHptwArbLLPTWPort = 1 132 hptw_req_arb.io.in(InHptwArbPTWPort).valid := ptw.io.hptw.req.valid 133 hptw_req_arb.io.in(InHptwArbPTWPort).bits.gvpn := ptw.io.hptw.req.bits.gvpn 134 hptw_req_arb.io.in(InHptwArbPTWPort).bits.id := ptw.io.hptw.req.bits.id 135 ptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbPTWPort).ready 136 137 hptw_req_arb.io.in(InHptwArbLLPTWPort).valid := llptw.io.hptw.req.valid 138 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.gvpn := llptw.io.hptw.req.bits.gvpn 139 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.id := llptw.io.hptw.req.bits.id 140 llptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbLLPTWPort).ready 141 142 val hptw_id = RegInit(0.U(log2Up(l2tlbParams.llptwsize).W)) 143 when(hptw_req_arb.io.out.valid) { 144 hptw_id := hptw_req_arb.io.out.bits.id 145 } 146 // arb2 input port 147 val InArbPTWPort = 0 148 val InArbMissQueuePort = 1 149 val InArbTlbPort = 2 150 val InArbPrefetchPort = 3 151 val InArbHPTWPort = 4 152 // NOTE: when cache out but miss and ptw doesnt accept, 153 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 154 arb1.io.out.ready := arb2.io.in(InArbTlbPort).ready 155 156 arb2.io.in(InArbPTWPort).valid := ptw.io.llptw.valid 157 arb2.io.in(InArbPTWPort).bits.vpn := ptw.io.llptw.bits.req_info.vpn 158 arb2.io.in(InArbPTWPort).bits.gvpn := ptw.io.llptw.bits.req_info.gvpn 159 arb2.io.in(InArbPTWPort).bits.s2xlate := ptw.io.llptw.bits.req_info.s2xlate 160 arb2.io.in(InArbPTWPort).bits.source := ptw.io.llptw.bits.req_info.source 161 ptw.io.llptw.ready := arb2.io.in(InArbPTWPort).ready 162 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 163 164 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 165 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 166 arb2.io.in(InArbTlbPort).bits.gvpn := arb1.io.out.bits.gvpn 167 arb2.io.in(InArbTlbPort).bits.s2xlate := arb1.io.out.bits.s2xlate 168 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 169 170 arb2.io.in(InArbHPTWPort).valid := hptw_req_arb.io.out.valid 171 arb2.io.in(InArbHPTWPort).bits.vpn := DontCare 172 arb2.io.in(InArbHPTWPort).bits.gvpn := hptw_req_arb.io.out.bits.gvpn 173 arb2.io.in(InArbHPTWPort).bits.s2xlate := "0b11".U 174 arb2.io.in(InArbHPTWPort).bits.source := DontCare 175 if (l2tlbParams.enablePrefetch) { 176 val prefetch = Module(new L2TlbPrefetch()) 177 val recv = cache.io.resp 178 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 179 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 180 prefetch.io.in.valid := recv.fire && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 181 recv.bits.prefetch) && recv.bits.isFirst 182 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 183 prefetch.io.sfence := sfence_dup(0) 184 prefetch.io.csr := csr_dup(0) 185 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 186 187 val isWriteL2TlbPrefetchTable = WireInit(Constantin.createRecord("isWriteL2TlbPrefetchTable" + p(XSCoreParamsKey).HartId.toString)) 188 val L2TlbPrefetchTable = ChiselDB.createTable("L2TlbPrefetch_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbPrefetchDB) 189 val L2TlbPrefetchDB = Wire(new L2TlbPrefetchDB) 190 L2TlbPrefetchDB.vpn := prefetch.io.out.bits.vpn 191 L2TlbPrefetchTable.log(L2TlbPrefetchDB, isWriteL2TlbPrefetchTable.orR && prefetch.io.out.fire, "L2TlbPrefetch", clock, reset) 192 } 193 arb2.io.out.ready := cache.io.req.ready 194 195 196 val mq_arb = Module(new Arbiter(new L2TlbInnerBundle, 2)) 197 mq_arb.io.in(0).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 198 (!cache.io.resp.bits.toFsm.l2Hit || cache.io.resp.bits.bypassed) && 199 !from_pre(cache.io.resp.bits.req_info.source) && 200 (cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst || !ptw.io.req.ready) 201 mq_arb.io.in(0).bits := cache.io.resp.bits.req_info 202 mq_arb.io.in(1) <> llptw.io.cache 203 missQueue.io.in <> mq_arb.io.out 204 missQueue.io.sfence := sfence_dup(6) 205 missQueue.io.csr := csr_dup(5) 206 207 blockmq.io.start := missQueue.io.out.fire 208 blockmq.io.enable := ptw.io.req.fire 209 210 llptw.io.in.valid := cache.io.resp.valid && 211 !cache.io.resp.bits.hit && 212 cache.io.resp.bits.toFsm.l2Hit && 213 !cache.io.resp.bits.bypassed && 214 !cache.io.resp.bits.isHptw 215 llptw.io.in.bits.req_info := cache.io.resp.bits.req_info 216 llptw.io.in.bits.ppn := cache.io.resp.bits.toFsm.ppn 217 llptw.io.sfence := sfence_dup(1) 218 llptw.io.csr := csr_dup(1) 219 220 cache.io.req.valid := arb2.io.out.valid 221 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 222 cache.io.req.bits.req_info.gvpn := arb2.io.out.bits.gvpn 223 cache.io.req.bits.req_info.s2xlate := arb2.io.out.bits.s2xlate 224 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 225 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 226 cache.io.req.bits.isHptw := arb2.io.chosen === InArbHPTWPort.U 227 cache.io.req.bits.hptwId := hptw_id 228 cache.io.req.bits.bypassed.map(_ := false.B) 229 cache.io.sfence := sfence_dup(2) 230 cache.io.csr := csr_dup(2) 231 cache.io.sfence_dup.zip(sfence_dup.drop(2).take(4)).map(s => s._1 := s._2) 232 cache.io.csr_dup.zip(csr_dup.drop(2).take(3)).map(c => c._1 := c._2) 233 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 234 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 235 Mux(cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed, llptw.io.in.ready, 236 Mux(cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst, mq_arb.io.in(0).ready, mq_arb.io.in(0).ready || ptw.io.req.ready))) 237 238 // NOTE: missQueue req has higher priority 239 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit && 240 !cache.io.resp.bits.bypassed && 241 !cache.io.resp.bits.isFirst && 242 !cache.io.resp.bits.isHptw 243 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 244 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 245 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 246 ptw.io.sfence := sfence_dup(7) 247 ptw.io.csr := csr_dup(6) 248 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 249 250 hptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.bypassed & cache.io.resp.bits.isHptw 251 hptw.io.req.bits.gvpn := cache.io.resp.bits.req_info.gvpn 252 hptw.io.req.bits.id := cache.io.resp.bits.toHptw.id 253 hptw.io.req.bits.l1Hit := cache.io.resp.bits.toHptw.l1Hit 254 hptw.io.req.bits.l2Hit := cache.io.resp.bits.toHptw.l2Hit 255 hptw.io.sfence := sfence_dup(8) 256 hptw.io.csr := csr_dup(7) 257 // mem req 258 def blockBytes_align(addr: UInt) = { 259 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 260 } 261 def addr_low_from_vpn(vpn: UInt) = { 262 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 263 } 264 def addr_low_from_paddr(paddr: UInt) = { 265 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 266 } 267 def from_llptw(id: UInt) = { 268 id < l2tlbParams.llptwsize.U 269 } 270 def from_ptw(id: UInt) = { 271 id === l2tlbParams.llptwsize.U 272 } 273 def from_hptw(id: UInt) = { 274 id === l2tlbParams.llptwsize.U + 1.U 275 } 276 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 277 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 278 for (i <- waiting_resp.indices) { 279 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 280 } 281 282 val llptw_out = llptw.io.out 283 val llptw_mem = llptw.io.mem 284 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 285 ptw.io.mem.mask := waiting_resp.slice(l2tlbParams.llptwsize, l2tlbParams.llptwsize+1) 286 hptw.io.mem.mask := waiting_resp.slice(l2tlbParams.llptwsize+1, l2tlbParams.llptwsize+2) 287 288 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 3)) 289 mem_arb.io.in(0) <> ptw.io.mem.req 290 mem_arb.io.in(1) <> llptw_mem.req 291 mem_arb.io.in(2) <> hptw.io.mem.req 292 mem_arb.io.out.ready := mem.a.ready && !flush 293 294 // assert, should not send mem access at same addr for twice. 295 val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info_dup(0).vpn, cache.io.refill.valid) 296 val last_resp_level = RegEnable(cache.io.refill.bits.level_dup(0), cache.io.refill.valid) 297 val last_resp_v = RegInit(false.B) 298 val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR || cache.io.refill.bits.sel_pte_dup(0).asTypeOf(new PteBundle).isAf() 299 when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 300 when (flush) { last_resp_v := false.B } 301 XSError(last_resp_v && cache.io.refill.valid && 302 (cache.io.refill.bits.req_info_dup(0).vpn === last_resp_vpn) && 303 (cache.io.refill.bits.level_dup(0) === last_resp_level), 304 "l2tlb should not access mem at same addr for twice") 305 // ATTENTION: this may wrongly assert when: a ptes is l2, last part is valid, 306 // but the current part is invalid, so one more mem access happened 307 // If this happened, remove the assert. 308 309 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 310 311 when (llptw.io.in.fire) { 312 // when enq miss queue, set the req_addr_low to receive the mem resp data part 313 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 314 } 315 when (mem_arb.io.out.fire) { 316 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 317 waiting_resp(mem_arb.io.out.bits.id) := true.B 318 } 319 // mem read 320 val memRead = edge.Get( 321 fromSource = mem_arb.io.out.bits.id, 322 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 323 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 324 lgSize = log2Up(l2tlbParams.blockBytes).U 325 )._2 326 mem.a.bits := memRead 327 mem.a.valid := mem_arb.io.out.valid && !flush 328 mem.a.bits.user.lift(ReqSourceKey).foreach(_ := MemReqSource.PTW.id.U) 329 mem.d.ready := true.B 330 // mem -> data buffer 331 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 332 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire) 333 val mem_resp_done = refill_helper._3 334 val mem_resp_from_llptw = from_llptw(mem.d.bits.source) 335 val mem_resp_from_ptw = from_ptw(mem.d.bits.source) 336 val mem_resp_from_hptw = from_hptw(mem.d.bits.source) 337 when (mem.d.valid) { 338 assert(mem.d.bits.source < MemReqWidth.U) 339 refill_data(refill_helper._4) := mem.d.bits.data 340 } 341 // refill_data_tmp is the wire fork of refill_data, but one cycle earlier 342 val refill_data_tmp = WireInit(refill_data) 343 refill_data_tmp(refill_helper._4) := mem.d.bits.data 344 345 // save only one pte for each id 346 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 347 val resp_pte = VecInit((0 until MemReqWidth).map(i => 348 if (i == l2tlbParams.llptwsize + 1) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && mem_resp_from_hptw) } 349 else if (i == l2tlbParams.llptwsize) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && mem_resp_from_ptw) } 350 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 351 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 352 )) 353 354 // save eight ptes for each id when sector tlb 355 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 356 val resp_pte_sector = VecInit((0 until MemReqWidth).map(i => 357 if (i == l2tlbParams.llptwsize + 1) {RegEnable(refill_data_tmp, mem_resp_done && mem_resp_from_hptw) } 358 else if (i == l2tlbParams.llptwsize) {RegEnable(refill_data_tmp, mem_resp_done && mem_resp_from_ptw) } 359 else { DataHoldBypass(refill_data, llptw_mem.buffer_it(i)) } 360 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 361 )) 362 363 // mem -> llptw 364 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_llptw 365 llptw_mem.resp.bits.id := DataHoldBypass(mem.d.bits.source, mem.d.valid) 366 // mem -> ptw 367 ptw.io.mem.req.ready := mem.a.ready 368 ptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_ptw 369 ptw.io.mem.resp.bits := resp_pte.slice(l2tlbParams.llptwsize, l2tlbParams.llptwsize + 1) 370 // mem -> hptw 371 hptw.io.mem.req.ready := mem.a.ready 372 hptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_hptw 373 hptw.io.mem.resp.bits := resp_pte.slice(l2tlbParams.llptwsize + 1, l2tlbParams.llptwsize + 2) 374 // mem -> cache 375 val refill_from_llptw = mem_resp_from_llptw 376 val refill_from_ptw = mem_resp_from_ptw 377 val refill_from_hptw = mem_resp_from_hptw 378 val refill_level = Mux(refill_from_llptw, 2.U, Mux(refill_from_ptw, RegEnable(ptw.io.refill.level, init = 0.U, ptw.io.mem.req.fire()), RegEnable(hptw.io.refill.level, init = 0.U, hptw.io.mem.req.fire()))) 379 val refill_valid = mem_resp_done && !flush && !flush_latch(mem.d.bits.source) 380 381 cache.io.refill.valid := RegNext(refill_valid, false.B) 382 cache.io.refill.bits.ptes := refill_data.asUInt 383 cache.io.refill.bits.req_info_dup.map(_ := RegEnable(Mux(refill_from_llptw, llptw_mem.refill, Mux(refill_from_ptw, ptw.io.refill.req_info, hptw.io.refill.req_info)), refill_valid)) 384 cache.io.refill.bits.level_dup.map(_ := RegEnable(refill_level, refill_valid)) 385 cache.io.refill.bits.levelOH(refill_level, refill_valid) 386 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source)))) 387 388 if (env.EnableDifftest) { 389 val difftest_ptw_addr = RegInit(VecInit(Seq.fill(MemReqWidth)(0.U(PAddrBits.W)))) 390 when (mem.a.valid) { 391 difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address 392 } 393 394 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) 395 difftest.coreid := io.hartId 396 difftest.index := 2.U 397 difftest.valid := cache.io.refill.valid 398 difftest.addr := difftest_ptw_addr(RegNext(mem.d.bits.source)) 399 difftest.data := refill_data.asTypeOf(difftest.data) 400 difftest.idtfr := DontCare 401 } 402 403 if (env.EnableDifftest) { 404 for (i <- 0 until PtwWidth) { 405 val difftest = DifftestModule(new DiffL2TLBEvent) 406 difftest.coreid := io.hartId 407 difftest.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.af 408 difftest.index := i.U 409 difftest.satp := io.csr.tlb.satp.ppn 410 difftest.vpn := Cat(io.tlb(i).resp.bits.entry.tag, 0.U(sectortlbwidth.W)) 411 for (j <- 0 until tlbcontiguous) { 412 difftest.ppn(j) := Cat(io.tlb(i).resp.bits.entry.ppn, io.tlb(i).resp.bits.ppn_low(j)) 413 difftest.valididx(j) := io.tlb(i).resp.bits.valididx(j) 414 } 415 difftest.perm := io.tlb(i).resp.bits.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 416 difftest.level := io.tlb(i).resp.bits.entry.level.getOrElse(0.U.asUInt) 417 difftest.pf := io.tlb(i).resp.bits.pf 418 } 419 } 420 421 // pmp 422 pmp_check(0).req <> ptw.io.pmp.req 423 ptw.io.pmp.resp <> pmp_check(0).resp 424 pmp_check(1).req <> llptw.io.pmp.req 425 llptw.io.pmp.resp <> pmp_check(1).resp 426 427 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 428 429 // hptw and page cache -> ptw and llptw 430 val HptwRespArbCachePort = 0 431 val HptwRespArbHptw = 0 432 hptw_resp_arb.io.in(HptwRespArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.isHptw 433 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.id := cache.io.resp.bits.toHptw.id 434 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.resp := cache.io.resp.bits.toHptw.resp 435 hptw_resp_arb.io.in(HptwRespArbHptw).valid := hptw.io.resp.valid 436 hptw_resp_arb.io.in(HptwRespArbHptw).bits.id := hptw.io.resp.bits.id 437 hptw_resp_arb.io.in(HptwRespArbHptw).bits.resp := hptw.io.resp.bits.resp 438 439 ptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id === FsmReqID.U 440 ptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 441 llptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id =/= FsmReqID.U 442 llptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 443 444 // Timing: Maybe need to do some optimization or even add one more cycle 445 for (i <- 0 until PtwWidth) { 446 mergeArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U 447 mergeArb(i).in(outArbCachePort).bits.s2xlate := cache.io.resp.bits.req_info.s2xlate 448 mergeArb(i).in(outArbCachePort).bits.s1Resp := cache.io.resp.bits.toTlb 449 mergeArb(i).in(outArbCachePort).bits.s2Resp := cache.io.resp.bits.toHptw.resp 450 mergeArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 451 mergeArb(i).in(outArbFsmPort).bits.s2xlate := ptw.io.resp.bits.s2xlate 452 mergeArb(i).in(outArbFsmPort).bits.s1Resp := ptw.io.resp.bits.resp 453 mergeArb(i).in(outArbFsmPort).bits.s2Resp := ptw.io.resp.bits.h_resp 454 mergeArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 455 mergeArb(i).in(outArbMqPort).bits.s2xlate := llptw_out.bits.req_info.s2xlate 456 mergeArb(i).in(outArbMqPort).bits.s1Resp := contiguous_pte_to_merge_ptwResp(resp_pte_sector(llptw_out.bits.id).asUInt, llptw_out.bits.req_info.vpn, llptw_out.bits.af, true) 457 mergeArb(i).in(outArbMqPort).bits.s2Resp := llptw_out.bits.h_resp 458 mergeArb(i).out.ready := outArb(i).in(0).ready 459 } 460 461 for (i <- 0 until PtwWidth) { 462 outArb(i).in(0).valid := mergeArb(i).out.valid 463 outArb(i).in(0).bits.s1Resp := merge_ptwResp_to_sector_ptwResp(mergeArb(i).out.bits.s1Resp) 464 outArb(i).in(0).bits.s2Resp := mergeArb(i).out.bits.s2Resp 465 } 466 467 // io.tlb.map(_.resp) <> outArb.map(_.out) 468 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 469 case (resp, out) => resp <> out 470 } 471 472 // sfence 473 when (flush) { 474 for (i <- 0 until MemReqWidth) { 475 when (waiting_resp(i)) { 476 flush_latch(i) := true.B 477 } 478 } 479 } 480 // mem -> control signal 481 // waiting_resp and sfence_latch will be reset when mem_resp_done 482 when (mem_resp_done) { 483 waiting_resp(mem.d.bits.source) := false.B 484 flush_latch(mem.d.bits.source) := false.B 485 } 486 487 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 488 sink.valid := source.valid && !block_signal 489 source.ready := sink.ready && !block_signal 490 sink.bits := source.bits 491 } 492 493 def get_part(data: Vec[UInt], index: UInt): UInt = { 494 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 495 inner_data(index) 496 } 497 498 // not_super means that this is a normal page 499 // valididx(i) will be all true when super page to be convenient for l1 tlb matching 500 def contiguous_pte_to_merge_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean, not_super: Boolean = true) : PtwMergeResp = { 501 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 502 val ptw_merge_resp = Wire(new PtwMergeResp()) 503 for (i <- 0 until tlbcontiguous) { 504 val pte_in = pte(64 * i + 63, 64 * i).asTypeOf(new PteBundle()) 505 val ptw_resp = Wire(new PtwMergeEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true)) 506 ptw_resp.ppn := pte_in.ppn(ppnLen - 1, sectortlbwidth) 507 ptw_resp.ppn_low := pte_in.ppn(sectortlbwidth - 1, 0) 508 ptw_resp.level.map(_ := 2.U) 509 ptw_resp.perm.map(_ := pte_in.getPerm()) 510 ptw_resp.tag := vpn(vpnLen - 1, sectortlbwidth) 511 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 512 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && (af || pte_in.isAf()) 513 ptw_resp.v := !ptw_resp.pf 514 ptw_resp.prefetch := DontCare 515 ptw_resp.asid := satp.asid 516 ptw_merge_resp.entry(i) := ptw_resp 517 } 518 ptw_merge_resp.pteidx := UIntToOH(vpn(sectortlbwidth - 1, 0)).asBools 519 ptw_merge_resp.not_super := not_super.B 520 ptw_merge_resp 521 } 522 523 def merge_ptwResp_to_sector_ptwResp(pte: PtwMergeResp) : PtwSectorResp = { 524 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 525 val ptw_sector_resp = Wire(new PtwSectorResp) 526 ptw_sector_resp.entry.tag := pte.entry(OHToUInt(pte.pteidx)).tag 527 ptw_sector_resp.entry.asid := pte.entry(OHToUInt(pte.pteidx)).asid 528 ptw_sector_resp.entry.ppn := pte.entry(OHToUInt(pte.pteidx)).ppn 529 ptw_sector_resp.entry.perm.map(_ := pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle))) 530 ptw_sector_resp.entry.level.map(_ := pte.entry(OHToUInt(pte.pteidx)).level.getOrElse(0.U(2.W))) 531 ptw_sector_resp.entry.prefetch := pte.entry(OHToUInt(pte.pteidx)).prefetch 532 ptw_sector_resp.entry.v := pte.entry(OHToUInt(pte.pteidx)).v 533 ptw_sector_resp.af := pte.entry(OHToUInt(pte.pteidx)).af 534 ptw_sector_resp.pf := pte.entry(OHToUInt(pte.pteidx)).pf 535 ptw_sector_resp.addr_low := OHToUInt(pte.pteidx) 536 ptw_sector_resp.pteidx := pte.pteidx 537 for (i <- 0 until tlbcontiguous) { 538 val ppn_equal = pte.entry(i).ppn === pte.entry(OHToUInt(pte.pteidx)).ppn 539 val perm_equal = pte.entry(i).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt === pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 540 val v_equal = pte.entry(i).v === pte.entry(OHToUInt(pte.pteidx)).v 541 val af_equal = pte.entry(i).af === pte.entry(OHToUInt(pte.pteidx)).af 542 val pf_equal = pte.entry(i).pf === pte.entry(OHToUInt(pte.pteidx)).pf 543 ptw_sector_resp.valididx(i) := (ppn_equal && perm_equal && v_equal && af_equal && pf_equal) || !pte.not_super 544 ptw_sector_resp.ppn_low(i) := pte.entry(i).ppn_low 545 } 546 ptw_sector_resp.valididx(OHToUInt(pte.pteidx)) := true.B 547 ptw_sector_resp 548 } 549 550 def outReady(source: UInt, port: Int): Bool = { 551 MuxLookup(source, true.B)((0 until PtwWidth).map(i => i.U -> mergeArb(i).in(port).ready)) 552 } 553 554 // debug info 555 for (i <- 0 until PtwWidth) { 556 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 557 } 558 XSDebug(p"[sfence] ${io.sfence}\n") 559 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 560 561 for (i <- 0 until PtwWidth) { 562 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire) 563 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 564 } 565 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 566 for (i <- 0 until (MemReqWidth + 1)) { 567 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 568 } 569 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 570 XSPerfAccumulate("mem_count", mem.a.fire) 571 for (i <- 0 until PtwWidth) { 572 XSPerfAccumulate(s"llptw_ppn_af${i}", mergeArb(i).in(outArbMqPort).valid && mergeArb(i).in(outArbMqPort).bits.entry(OHToUInt(mergeArb(i).in(outArbMqPort).bits.pteidx)).af && !llptw_out.bits.af) 573 XSPerfAccumulate(s"access_fault${i}", io.tlb(i).resp.fire && io.tlb(i).resp.bits.af) 574 } 575 576 // print configs 577 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 578 579 // time out assert 580 for (i <- 0 until MemReqWidth) { 581 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 582 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 583 } 584 585 586 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 587 generatePerfEvent() 588 589 val isWriteL1TlbTable = WireInit(Constantin.createRecord("isWriteL1TlbTable" + p(XSCoreParamsKey).HartId.toString)) 590 val L1TlbTable = ChiselDB.createTable("L1Tlb_hart" + p(XSCoreParamsKey).HartId.toString, new L1TlbDB) 591 val ITlbReqDB, DTlbReqDB, ITlbRespDB, DTlbRespDB = Wire(new L1TlbDB) 592 ITlbReqDB.vpn := io.tlb(0).req(0).bits.vpn 593 DTlbReqDB.vpn := io.tlb(1).req(0).bits.vpn 594 ITlbRespDB.vpn := io.tlb(0).resp.bits.entry.tag 595 DTlbRespDB.vpn := io.tlb(1).resp.bits.entry.tag 596 L1TlbTable.log(ITlbReqDB, isWriteL1TlbTable.orR && io.tlb(0).req(0).fire, "ITlbReq", clock, reset) 597 L1TlbTable.log(DTlbReqDB, isWriteL1TlbTable.orR && io.tlb(1).req(0).fire, "DTlbReq", clock, reset) 598 L1TlbTable.log(ITlbRespDB, isWriteL1TlbTable.orR && io.tlb(0).resp.fire, "ITlbResp", clock, reset) 599 L1TlbTable.log(DTlbRespDB, isWriteL1TlbTable.orR && io.tlb(1).resp.fire, "DTlbResp", clock, reset) 600 601 val isWritePageCacheTable = WireInit(Constantin.createRecord("isWritePageCacheTable" + p(XSCoreParamsKey).HartId.toString)) 602 val PageCacheTable = ChiselDB.createTable("PageCache_hart" + p(XSCoreParamsKey).HartId.toString, new PageCacheDB) 603 val PageCacheDB = Wire(new PageCacheDB) 604 PageCacheDB.vpn := Cat(cache.io.resp.bits.toTlb.entry(0).tag, OHToUInt(cache.io.resp.bits.toTlb.pteidx)) 605 PageCacheDB.source := cache.io.resp.bits.req_info.source 606 PageCacheDB.bypassed := cache.io.resp.bits.bypassed 607 PageCacheDB.is_first := cache.io.resp.bits.isFirst 608 PageCacheDB.prefetched := cache.io.resp.bits.toTlb.entry(0).prefetch 609 PageCacheDB.prefetch := cache.io.resp.bits.prefetch 610 PageCacheDB.l2Hit := cache.io.resp.bits.toFsm.l2Hit 611 PageCacheDB.l1Hit := cache.io.resp.bits.toFsm.l1Hit 612 PageCacheDB.hit := cache.io.resp.bits.hit 613 PageCacheTable.log(PageCacheDB, isWritePageCacheTable.orR && cache.io.resp.fire, "PageCache", clock, reset) 614 615 val isWritePTWTable = WireInit(Constantin.createRecord("isWritePTWTable" + p(XSCoreParamsKey).HartId.toString)) 616 val PTWTable = ChiselDB.createTable("PTW_hart" + p(XSCoreParamsKey).HartId.toString, new PTWDB) 617 val PTWReqDB, PTWRespDB, LLPTWReqDB, LLPTWRespDB = Wire(new PTWDB) 618 PTWReqDB.vpn := ptw.io.req.bits.req_info.vpn 619 PTWReqDB.source := ptw.io.req.bits.req_info.source 620 PTWRespDB.vpn := ptw.io.refill.req_info.vpn 621 PTWRespDB.source := ptw.io.refill.req_info.source 622 LLPTWReqDB.vpn := llptw.io.in.bits.req_info.vpn 623 LLPTWReqDB.source := llptw.io.in.bits.req_info.source 624 LLPTWRespDB.vpn := llptw.io.mem.refill.vpn 625 LLPTWRespDB.source := llptw.io.mem.refill.source 626 PTWTable.log(PTWReqDB, isWritePTWTable.orR && ptw.io.req.fire, "PTWReq", clock, reset) 627 PTWTable.log(PTWRespDB, isWritePTWTable.orR && ptw.io.mem.resp.fire, "PTWResp", clock, reset) 628 PTWTable.log(LLPTWReqDB, isWritePTWTable.orR && llptw.io.in.fire, "LLPTWReq", clock, reset) 629 PTWTable.log(LLPTWRespDB, isWritePTWTable.orR && llptw.io.mem.resp.fire, "LLPTWResp", clock, reset) 630 631 val isWriteL2TlbMissQueueTable = WireInit(Constantin.createRecord("isWriteL2TlbMissQueueTable" + p(XSCoreParamsKey).HartId.toString)) 632 val L2TlbMissQueueTable = ChiselDB.createTable("L2TlbMissQueue_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbMissQueueDB) 633 val L2TlbMissQueueInDB, L2TlbMissQueueOutDB = Wire(new L2TlbMissQueueDB) 634 L2TlbMissQueueInDB.vpn := missQueue.io.in.bits.vpn 635 L2TlbMissQueueOutDB.vpn := missQueue.io.out.bits.vpn 636 L2TlbMissQueueTable.log(L2TlbMissQueueInDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.in.fire, "L2TlbMissQueueIn", clock, reset) 637 L2TlbMissQueueTable.log(L2TlbMissQueueOutDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.out.fire, "L2TlbMissQueueOut", clock, reset) 638} 639 640/** BlockHelper, block missqueue, not to send too many req to cache 641 * Parameter: 642 * enable: enable BlockHelper, mq should not send too many reqs 643 * start: when miss queue out fire and need, block miss queue's out 644 * block: block miss queue's out 645 * latency: last missqueue out's cache access latency 646 */ 647class BlockHelper(latency: Int)(implicit p: Parameters) extends XSModule { 648 val io = IO(new Bundle { 649 val enable = Input(Bool()) 650 val start = Input(Bool()) 651 val block = Output(Bool()) 652 }) 653 654 val count = RegInit(0.U(log2Ceil(latency).W)) 655 val valid = RegInit(false.B) 656 val work = RegInit(true.B) 657 658 io.block := valid 659 660 when (io.start && work) { valid := true.B } 661 when (valid) { count := count + 1.U } 662 when (count === (latency.U) || io.enable) { 663 valid := false.B 664 work := io.enable 665 count := 0.U 666 } 667} 668 669class PTEHelper() extends ExtModule { 670 val clock = IO(Input(Clock())) 671 val enable = IO(Input(Bool())) 672 val satp = IO(Input(UInt(64.W))) 673 val vpn = IO(Input(UInt(64.W))) 674 val pte = IO(Output(UInt(64.W))) 675 val level = IO(Output(UInt(8.W))) 676 val pf = IO(Output(UInt(8.W))) 677} 678 679class PTWDelayN[T <: Data](gen: T, n: Int, flush: Bool) extends Module { 680 val io = IO(new Bundle() { 681 val in = Input(gen) 682 val out = Output(gen) 683 val ptwflush = Input(flush.cloneType) 684 }) 685 val out = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 686 val t = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 687 out(0) := io.in 688 if (n == 1) { 689 io.out := out(0) 690 } else { 691 when (io.ptwflush) { 692 for (i <- 0 until n) { 693 t(i) := 0.U.asTypeOf(gen) 694 out(i) := 0.U.asTypeOf(gen) 695 } 696 io.out := 0.U.asTypeOf(gen) 697 } .otherwise { 698 for (i <- 1 until n) { 699 t(i-1) := out(i-1) 700 out(i) := t(i-1) 701 } 702 io.out := out(n-1) 703 } 704 } 705} 706 707object PTWDelayN { 708 def apply[T <: Data](in: T, n: Int, flush: Bool): T = { 709 val delay = Module(new PTWDelayN(in.cloneType, n, flush)) 710 delay.io.in := in 711 delay.io.ptwflush := flush 712 delay.io.out 713 } 714} 715 716class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 717 val io = IO(new L2TLBIO) 718 val flush = VecInit(Seq.fill(PtwWidth)(false.B)) 719 flush(0) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, itlbParams.fenceDelay) 720 flush(1) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, ldtlbParams.fenceDelay) 721 for (i <- 0 until PtwWidth) { 722 val helper = Module(new PTEHelper()) 723 helper.clock := clock 724 helper.satp := io.csr.tlb.satp.ppn 725 726 if (coreParams.softPTWDelay == 1) { 727 helper.enable := io.tlb(i).req(0).fire 728 helper.vpn := io.tlb(i).req(0).bits.vpn 729 } else { 730 helper.enable := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay - 1, flush(i)) 731 helper.vpn := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay - 1, flush(i)) 732 } 733 734 val pte = helper.pte.asTypeOf(new PteBundle) 735 val level = helper.level 736 val pf = helper.pf 737 val empty = RegInit(true.B) 738 when (io.tlb(i).req(0).fire) { 739 empty := false.B 740 } .elsewhen (io.tlb(i).resp.fire || flush(i)) { 741 empty := true.B 742 } 743 744 io.tlb(i).req(0).ready := empty || io.tlb(i).resp.fire 745 io.tlb(i).resp.valid := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay, flush(i)) 746 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 747 io.tlb(i).resp.bits.entry.tag := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay, flush(i)) 748 io.tlb(i).resp.bits.entry.ppn := pte.ppn 749 io.tlb(i).resp.bits.entry.perm.map(_ := pte.getPerm()) 750 io.tlb(i).resp.bits.entry.level.map(_ := level) 751 io.tlb(i).resp.bits.pf := pf 752 io.tlb(i).resp.bits.af := DontCare // TODO: implement it 753 io.tlb(i).resp.bits.entry.v := !pf 754 io.tlb(i).resp.bits.entry.prefetch := DontCare 755 io.tlb(i).resp.bits.entry.asid := io.csr.tlb.satp.asid 756 } 757} 758 759class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 760 override def shouldBeInlined: Boolean = false 761 val useSoftPTW = coreParams.softPTW 762 val node = if (!useSoftPTW) TLIdentityNode() else null 763 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 764 if (!useSoftPTW) { 765 node := ptw.node 766 } 767 768 class L2TLBWrapperImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) with HasPerfEvents { 769 val io = IO(new L2TLBIO) 770 val perfEvents = if (useSoftPTW) { 771 val fake_ptw = Module(new FakePTW()) 772 io <> fake_ptw.io 773 Seq() 774 } 775 else { 776 io <> ptw.module.io 777 ptw.module.getPerfEvents 778 } 779 generatePerfEvent() 780 } 781 782 lazy val module = new L2TLBWrapperImp(this) 783} 784