1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31import difftest._ 32 33class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 34 override def shouldBeInlined: Boolean = false 35 36 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 37 clients = Seq(TLMasterParameters.v1( 38 "ptw", 39 sourceId = IdRange(0, MemReqWidth) 40 )), 41 requestFields = Seq(ReqSourceField()) 42 ))) 43 44 lazy val module = new L2TLBImp(this) 45} 46 47class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 48 49 val (mem, edge) = outer.node.out.head 50 51 val io = IO(new L2TLBIO) 52 val difftestIO = IO(new Bundle() { 53 val ptwResp = Output(Bool()) 54 val ptwAddr = Output(UInt(64.W)) 55 val ptwData = Output(Vec(4, UInt(64.W))) 56 }) 57 58 /* Ptw processes multiple requests 59 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 60 * miss queue itlb dtlb 61 * | | | 62 * ------arbiter------ 63 * | 64 * l1 - l2 - l3 - sp 65 * | 66 * ------------------------------------------- 67 * miss | queue | hit 68 * [][][][][][] | 69 * | | 70 * state machine accessing mem | 71 * | | 72 * ---------------arbiter--------------------- 73 * | | 74 * itlb dtlb 75 */ 76 77 difftestIO <> DontCare 78 79 val sfence_tmp = DelayN(io.sfence, 1) 80 val csr_tmp = DelayN(io.csr.tlb, 1) 81 val sfence_dup = Seq.fill(9)(RegNext(sfence_tmp)) 82 val csr_dup = Seq.fill(8)(RegNext(csr_tmp)) 83 val satp = csr_dup(0).satp 84 val vsatp = csr_dup(0).vsatp 85 val hgatp = csr_dup(0).hgatp 86 val priv = csr_dup(0).priv 87 val flush = sfence_dup(0).valid || satp.changed || vsatp.changed || hgatp.changed 88 89 val pmp = Module(new PMP()) 90 val pmp_check = VecInit(Seq.fill(3)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 91 pmp.io.distribute_csr := io.csr.distribute_csr 92 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 93 94 val missQueue = Module(new L2TlbMissQueue) 95 val cache = Module(new PtwCache) 96 val ptw = Module(new PTW) 97 val hptw = Module(new HPTW) 98 val llptw = Module(new LLPTW) 99 val blockmq = Module(new BlockHelper(3)) 100 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 101 val arb2 = Module(new Arbiter(new Bundle { 102 val vpn = UInt(vpnLen.W) 103 val s2xlate = UInt(2.W) 104 val source = UInt(bSourceWidth.W) 105 }, (if (l2tlbParams.enablePrefetch) 4 else 3) + (if(HasHExtension) 1 else 0))) 106 val hptw_req_arb = Module(new Arbiter(new Bundle { 107 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 108 val source = UInt(bSourceWidth.W) 109 val gvpn = UInt(vpnLen.W) 110 }, 2)) 111 val hptw_resp_arb = Module(new Arbiter(new Bundle { 112 val resp = new HptwResp() 113 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 114 }, 2)) 115 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 116 val s2xlate = UInt(2.W) 117 val s1 = new PtwSectorResp () 118 val s2 = new HptwResp() 119 }, 1)).io) 120 val mergeArb = (0 until PtwWidth).map(i => Module(new Arbiter(new Bundle { 121 val s2xlate = UInt(2.W) 122 val s1 = new PtwMergeResp() 123 val s2 = new HptwResp() 124 }, 3)).io) 125 val outArbCachePort = 0 126 val outArbFsmPort = 1 127 val outArbMqPort = 2 128 129 // hptw arb input port 130 val InHptwArbPTWPort = 0 131 val InHptwArbLLPTWPort = 1 132 hptw_req_arb.io.in(InHptwArbPTWPort).valid := ptw.io.hptw.req.valid 133 hptw_req_arb.io.in(InHptwArbPTWPort).bits.gvpn := ptw.io.hptw.req.bits.gvpn 134 hptw_req_arb.io.in(InHptwArbPTWPort).bits.id := ptw.io.hptw.req.bits.id 135 hptw_req_arb.io.in(InHptwArbPTWPort).bits.source := ptw.io.hptw.req.bits.source 136 ptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbPTWPort).ready 137 138 hptw_req_arb.io.in(InHptwArbLLPTWPort).valid := llptw.io.hptw.req.valid 139 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.gvpn := llptw.io.hptw.req.bits.gvpn 140 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.id := llptw.io.hptw.req.bits.id 141 hptw_req_arb.io.in(InHptwArbLLPTWPort).bits.source := llptw.io.hptw.req.bits.source 142 llptw.io.hptw.req.ready := hptw_req_arb.io.in(InHptwArbLLPTWPort).ready 143 144 // arb2 input port 145 val InArbPTWPort = 0 146 val InArbMissQueuePort = 1 147 val InArbTlbPort = 2 148 val InArbPrefetchPort = 3 149 val InArbHPTWPort = 4 150 // NOTE: when cache out but miss and ptw doesnt accept, 151 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 152 153 154 arb2.io.in(InArbPTWPort).valid := ptw.io.llptw.valid 155 arb2.io.in(InArbPTWPort).bits.vpn := ptw.io.llptw.bits.req_info.vpn 156 arb2.io.in(InArbPTWPort).bits.s2xlate := ptw.io.llptw.bits.req_info.s2xlate 157 arb2.io.in(InArbPTWPort).bits.source := ptw.io.llptw.bits.req_info.source 158 ptw.io.llptw.ready := arb2.io.in(InArbPTWPort).ready 159 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 160 161 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 162 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 163 arb2.io.in(InArbTlbPort).bits.s2xlate := arb1.io.out.bits.s2xlate 164 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 165 arb1.io.out.ready := arb2.io.in(InArbTlbPort).ready 166 167 arb2.io.in(InArbHPTWPort).valid := hptw_req_arb.io.out.valid 168 arb2.io.in(InArbHPTWPort).bits.vpn := hptw_req_arb.io.out.bits.gvpn 169 arb2.io.in(InArbHPTWPort).bits.s2xlate := onlyStage2 170 arb2.io.in(InArbHPTWPort).bits.source := hptw_req_arb.io.out.bits.source 171 hptw_req_arb.io.out.ready := arb2.io.in(InArbHPTWPort).ready 172 if (l2tlbParams.enablePrefetch) { 173 val prefetch = Module(new L2TlbPrefetch()) 174 val recv = cache.io.resp 175 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 176 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 177 prefetch.io.in.valid := recv.fire && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 178 recv.bits.prefetch) && recv.bits.isFirst 179 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 180 prefetch.io.sfence := sfence_dup(0) 181 prefetch.io.csr := csr_dup(0) 182 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 183 184 val isWriteL2TlbPrefetchTable = WireInit(Constantin.createRecord("isWriteL2TlbPrefetchTable" + p(XSCoreParamsKey).HartId.toString)) 185 val L2TlbPrefetchTable = ChiselDB.createTable("L2TlbPrefetch_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbPrefetchDB) 186 val L2TlbPrefetchDB = Wire(new L2TlbPrefetchDB) 187 L2TlbPrefetchDB.vpn := prefetch.io.out.bits.vpn 188 L2TlbPrefetchTable.log(L2TlbPrefetchDB, isWriteL2TlbPrefetchTable.orR && prefetch.io.out.fire, "L2TlbPrefetch", clock, reset) 189 } 190 arb2.io.out.ready := cache.io.req.ready 191 192 193 val mq_arb = Module(new Arbiter(new L2TlbInnerBundle, 2)) 194 mq_arb.io.in(0).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 195 (!cache.io.resp.bits.toFsm.l2Hit || cache.io.resp.bits.bypassed) && 196 !from_pre(cache.io.resp.bits.req_info.source) && !cache.io.resp.bits.isHptw && 197 (cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst || !ptw.io.req.ready) 198 mq_arb.io.in(0).bits := cache.io.resp.bits.req_info 199 mq_arb.io.in(1) <> llptw.io.cache 200 missQueue.io.in <> mq_arb.io.out 201 missQueue.io.sfence := sfence_dup(6) 202 missQueue.io.csr := csr_dup(5) 203 204 blockmq.io.start := missQueue.io.out.fire 205 blockmq.io.enable := ptw.io.req.fire 206 207 llptw.io.in.valid := cache.io.resp.valid && 208 !cache.io.resp.bits.hit && 209 cache.io.resp.bits.toFsm.l2Hit && 210 !cache.io.resp.bits.bypassed && 211 !cache.io.resp.bits.isHptw 212 llptw.io.in.bits.req_info := cache.io.resp.bits.req_info 213 llptw.io.in.bits.ppn := cache.io.resp.bits.toFsm.ppn 214 llptw.io.sfence := sfence_dup(1) 215 llptw.io.csr := csr_dup(1) 216 217 cache.io.req.valid := arb2.io.out.valid 218 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 219 cache.io.req.bits.req_info.s2xlate := arb2.io.out.bits.s2xlate 220 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 221 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 222 cache.io.req.bits.isHptw := arb2.io.chosen === InArbHPTWPort.U 223 cache.io.req.bits.hptwId := hptw_req_arb.io.out.bits.id 224 cache.io.req.bits.bypassed.map(_ := false.B) 225 cache.io.sfence := sfence_dup(2) 226 cache.io.csr := csr_dup(2) 227 cache.io.sfence_dup.zip(sfence_dup.drop(2).take(4)).map(s => s._1 := s._2) 228 cache.io.csr_dup.zip(csr_dup.drop(2).take(3)).map(c => c._1 := c._2) 229 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 230 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 231 Mux(cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed, llptw.io.in.ready, 232 Mux(cache.io.resp.bits.bypassed || cache.io.resp.bits.isFirst, mq_arb.io.in(0).ready, mq_arb.io.in(0).ready || ptw.io.req.ready))) 233 234 // NOTE: missQueue req has higher priority 235 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit && 236 !cache.io.resp.bits.bypassed && 237 !cache.io.resp.bits.isFirst && 238 !cache.io.resp.bits.isHptw 239 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 240 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 241 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 242 ptw.io.req.bits.stage1Hit := cache.io.resp.bits.toFsm.stage1Hit 243 ptw.io.req.bits.stage1 := cache.io.resp.bits.toTlb 244 ptw.io.sfence := sfence_dup(7) 245 ptw.io.csr := csr_dup(6) 246 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 247 248 hptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.bypassed & cache.io.resp.bits.isHptw 249 hptw.io.req.bits.gvpn := cache.io.resp.bits.req_info.vpn 250 hptw.io.req.bits.id := cache.io.resp.bits.toHptw.id 251 hptw.io.req.bits.source := cache.io.resp.bits.req_info.source 252 hptw.io.req.bits.l1Hit := cache.io.resp.bits.toHptw.l1Hit 253 hptw.io.req.bits.l2Hit := cache.io.resp.bits.toHptw.l2Hit 254 hptw.io.req.bits.ppn := cache.io.resp.bits.toHptw.ppn 255 hptw.io.sfence := sfence_dup(8) 256 hptw.io.csr := csr_dup(7) 257 // mem req 258 def blockBytes_align(addr: UInt) = { 259 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 260 } 261 def addr_low_from_vpn(vpn: UInt) = { 262 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 263 } 264 def addr_low_from_paddr(paddr: UInt) = { 265 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 266 } 267 def from_llptw(id: UInt) = { 268 id < l2tlbParams.llptwsize.U 269 } 270 def from_ptw(id: UInt) = { 271 id === l2tlbParams.llptwsize.U 272 } 273 def from_hptw(id: UInt) = { 274 id === l2tlbParams.llptwsize.U + 1.U 275 } 276 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 277 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 278 for (i <- waiting_resp.indices) { 279 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 280 } 281 282 val llptw_out = llptw.io.out 283 val llptw_mem = llptw.io.mem 284 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 285 ptw.io.mem.mask := waiting_resp.apply(l2tlbParams.llptwsize) 286 hptw.io.mem.mask := waiting_resp.apply(l2tlbParams.llptwsize + 1) 287 288 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 3)) 289 mem_arb.io.in(0) <> ptw.io.mem.req 290 mem_arb.io.in(1) <> llptw_mem.req 291 mem_arb.io.in(2) <> hptw.io.mem.req 292 mem_arb.io.out.ready := mem.a.ready && !flush 293 294 // assert, should not send mem access at same addr for twice. 295 val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info_dup(0).vpn, cache.io.refill.valid) 296 val last_resp_s2xlate = RegEnable(cache.io.refill.bits.req_info_dup(0).s2xlate, cache.io.refill.valid) 297 val last_resp_level = RegEnable(cache.io.refill.bits.level_dup(0), cache.io.refill.valid) 298 val last_resp_v = RegInit(false.B) 299 val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR || cache.io.refill.bits.sel_pte_dup(0).asTypeOf(new PteBundle).isAf() 300 when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 301 when (flush) { last_resp_v := false.B } 302 XSError(last_resp_v && cache.io.refill.valid && 303 (cache.io.refill.bits.req_info_dup(0).vpn === last_resp_vpn) && 304 (cache.io.refill.bits.level_dup(0) === last_resp_level) && 305 (cache.io.refill.bits.req_info_dup(0).s2xlate === last_resp_s2xlate), 306 "l2tlb should not access mem at same addr for twice") 307 // ATTENTION: this may wrongly assert when: a ptes is l2, last part is valid, 308 // but the current part is invalid, so one more mem access happened 309 // If this happened, remove the assert. 310 311 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 312 313 when (llptw.io.in.fire) { 314 // when enq miss queue, set the req_addr_low to receive the mem resp data part 315 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 316 } 317 when (mem_arb.io.out.fire) { 318 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 319 waiting_resp(mem_arb.io.out.bits.id) := true.B 320 } 321 // mem read 322 val memRead = edge.Get( 323 fromSource = mem_arb.io.out.bits.id, 324 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 325 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 326 lgSize = log2Up(l2tlbParams.blockBytes).U 327 )._2 328 mem.a.bits := memRead 329 mem.a.valid := mem_arb.io.out.valid && !flush 330 mem.a.bits.user.lift(ReqSourceKey).foreach(_ := MemReqSource.PTW.id.U) 331 mem.d.ready := true.B 332 // mem -> data buffer 333 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 334 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire) 335 val mem_resp_done = refill_helper._3 336 val mem_resp_from_llptw = from_llptw(mem.d.bits.source) 337 val mem_resp_from_ptw = from_ptw(mem.d.bits.source) 338 val mem_resp_from_hptw = from_hptw(mem.d.bits.source) 339 when (mem.d.valid) { 340 assert(mem.d.bits.source < MemReqWidth.U) 341 refill_data(refill_helper._4) := mem.d.bits.data 342 } 343 // refill_data_tmp is the wire fork of refill_data, but one cycle earlier 344 val refill_data_tmp = WireInit(refill_data) 345 refill_data_tmp(refill_helper._4) := mem.d.bits.data 346 347 // save only one pte for each id 348 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 349 val resp_pte = VecInit((0 until MemReqWidth).map(i => 350 if (i == l2tlbParams.llptwsize + 1) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && mem_resp_from_hptw) } 351 else if (i == l2tlbParams.llptwsize) {RegEnable(get_part(refill_data_tmp, req_addr_low(i)), mem_resp_done && mem_resp_from_ptw) } 352 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 353 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 354 )) 355 356 // save eight ptes for each id when sector tlb 357 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 358 val resp_pte_sector = VecInit((0 until MemReqWidth).map(i => 359 if (i == l2tlbParams.llptwsize + 1) {RegEnable(refill_data_tmp, mem_resp_done && mem_resp_from_hptw) } 360 else if (i == l2tlbParams.llptwsize) {RegEnable(refill_data_tmp, mem_resp_done && mem_resp_from_ptw) } 361 else { DataHoldBypass(refill_data, llptw_mem.buffer_it(i)) } 362 // llptw could not use refill_data_tmp, because enq bypass's result works at next cycle 363 )) 364 365 // mem -> llptw 366 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_llptw 367 llptw_mem.resp.bits.id := DataHoldBypass(mem.d.bits.source, mem.d.valid) 368 llptw_mem.resp.bits.value := resp_pte.apply(mem.d.bits.source) 369 // mem -> ptw 370 ptw.io.mem.req.ready := mem.a.ready 371 ptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_ptw 372 ptw.io.mem.resp.bits := resp_pte.apply(l2tlbParams.llptwsize) 373 // mem -> hptw 374 hptw.io.mem.req.ready := mem.a.ready 375 hptw.io.mem.resp.valid := mem_resp_done && mem_resp_from_hptw 376 hptw.io.mem.resp.bits := resp_pte.apply(l2tlbParams.llptwsize + 1) 377 // mem -> cache 378 val refill_from_llptw = mem_resp_from_llptw 379 val refill_from_ptw = mem_resp_from_ptw 380 val refill_from_hptw = mem_resp_from_hptw 381 val refill_level = Mux(refill_from_llptw, 2.U, Mux(refill_from_ptw, RegEnable(ptw.io.refill.level, 0.U, ptw.io.mem.req.fire), RegEnable(hptw.io.refill.level, 0.U, hptw.io.mem.req.fire))) 382 val refill_valid = mem_resp_done && !flush && !flush_latch(mem.d.bits.source) 383 384 cache.io.refill.valid := RegNext(refill_valid, false.B) 385 cache.io.refill.bits.ptes := refill_data.asUInt 386 cache.io.refill.bits.req_info_dup.map(_ := RegEnable(Mux(refill_from_llptw, llptw_mem.refill, Mux(refill_from_ptw, ptw.io.refill.req_info, hptw.io.refill.req_info)), refill_valid)) 387 cache.io.refill.bits.level_dup.map(_ := RegEnable(refill_level, refill_valid)) 388 cache.io.refill.bits.levelOH(refill_level, refill_valid) 389 cache.io.refill.bits.sel_pte_dup.map(_ := RegNext(sel_data(refill_data_tmp.asUInt, req_addr_low(mem.d.bits.source)))) 390 391 if (env.EnableDifftest) { 392 val difftest_ptw_addr = RegInit(VecInit(Seq.fill(MemReqWidth)(0.U(PAddrBits.W)))) 393 when (mem.a.valid) { 394 difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address 395 } 396 397 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) 398 difftest.coreid := io.hartId 399 difftest.index := 2.U 400 difftest.valid := cache.io.refill.valid 401 difftest.addr := difftest_ptw_addr(RegNext(mem.d.bits.source)) 402 difftest.data := refill_data.asTypeOf(difftest.data) 403 difftest.idtfr := DontCare 404 } 405 406 if (env.EnableDifftest) { 407 for (i <- 0 until PtwWidth) { 408 val difftest = DifftestModule(new DiffL2TLBEvent) 409 difftest.clock := clock 410 difftest.coreid := p(XSCoreParamsKey).HartId.asUInt 411 difftest.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.s1.af && !io.tlb(i).resp.bits.s2.gaf 412 difftest.index := i.U 413 difftest.vpn := Cat(io.tlb(i).resp.bits.s1.entry.tag, 0.U(sectortlbwidth.W)) 414 for (j <- 0 until tlbcontiguous) { 415 difftest.ppn(j) := Cat(io.tlb(i).resp.bits.entry.ppn, io.tlb(i).resp.bits.ppn_low(j)) 416 difftest.valididx(j) := io.tlb(i).resp.bits.valididx(j) 417 difftest.pteidx(j) := io.tlb(i).resp.bits.s1.pteidx(j) 418 } 419 difftest.perm := io.tlb(i).resp.bits.s1.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 420 difftest.level := io.tlb(i).resp.bits.s1.entry.level.getOrElse(0.U.asUInt) 421 difftest.pf := io.tlb(i).resp.bits.s1.pf 422 difftest.satp := Cat(io.csr.tlb.satp.mode, io.csr.tlb.satp.asid, io.csr.tlb.satp.ppn) 423 difftest.vsatp := Cat(io.csr.tlb.vsatp.mode, io.csr.tlb.vsatp.asid, io.csr.tlb.vsatp.ppn) 424 difftest.hgatp := Cat(io.csr.tlb.hgatp.mode, io.csr.tlb.hgatp.asid, io.csr.tlb.hgatp.ppn) 425 difftest.gvpn := io.tlb(i).resp.bits.s2.entry.tag 426 difftest.g_perm := io.tlb(i).resp.bits.s2.entry.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 427 difftest.g_level := io.tlb(i).resp.bits.s2.entry.level.getOrElse(0.U.asUInt) 428 difftest.s2ppn := io.tlb(i).resp.bits.s2.entry.ppn 429 difftest.gpf := io.tlb(i).resp.bits.s2.gpf 430 difftest.s2xlate := io.tlb(i).resp.bits.s2xlate 431 } 432 } 433 434 // pmp 435 pmp_check(0).req <> ptw.io.pmp.req 436 ptw.io.pmp.resp <> pmp_check(0).resp 437 pmp_check(1).req <> llptw.io.pmp.req 438 llptw.io.pmp.resp <> pmp_check(1).resp 439 pmp_check(2).req <> hptw.io.pmp.req 440 hptw.io.pmp.resp <> pmp_check(2).resp 441 442 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 443 444 // hptw and page cache -> ptw and llptw 445 val HptwRespArbCachePort = 0 446 val HptwRespArbHptw = 1 447 hptw_resp_arb.io.in(HptwRespArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.isHptw 448 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.id := cache.io.resp.bits.toHptw.id 449 hptw_resp_arb.io.in(HptwRespArbCachePort).bits.resp := cache.io.resp.bits.toHptw.resp 450 hptw_resp_arb.io.in(HptwRespArbHptw).valid := hptw.io.resp.valid 451 hptw_resp_arb.io.in(HptwRespArbHptw).bits.id := hptw.io.resp.bits.id 452 hptw_resp_arb.io.in(HptwRespArbHptw).bits.resp := hptw.io.resp.bits.resp 453 454 ptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id === FsmReqID.U 455 ptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 456 llptw.io.hptw.resp.valid := hptw_resp_arb.io.out.valid && hptw_resp_arb.io.out.bits.id =/= FsmReqID.U 457 llptw.io.hptw.resp.bits.id := hptw_resp_arb.io.out.bits.id 458 llptw.io.hptw.resp.bits.h_resp := hptw_resp_arb.io.out.bits.resp 459 hptw_resp_arb.io.out.ready := true.B 460 461 // Timing: Maybe need to do some optimization or even add one more cycle 462 for (i <- 0 until PtwWidth) { 463 mergeArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U && !cache.io.resp.bits.isHptw 464 mergeArb(i).in(outArbCachePort).bits.s2xlate := cache.io.resp.bits.req_info.s2xlate 465 mergeArb(i).in(outArbCachePort).bits.s1 := cache.io.resp.bits.toTlb 466 mergeArb(i).in(outArbCachePort).bits.s2 := cache.io.resp.bits.toHptw.resp 467 mergeArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 468 mergeArb(i).in(outArbFsmPort).bits.s2xlate := ptw.io.resp.bits.s2xlate 469 mergeArb(i).in(outArbFsmPort).bits.s1 := ptw.io.resp.bits.resp 470 mergeArb(i).in(outArbFsmPort).bits.s2 := ptw.io.resp.bits.h_resp 471 mergeArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 472 mergeArb(i).in(outArbMqPort).bits.s2xlate := llptw_out.bits.req_info.s2xlate 473 mergeArb(i).in(outArbMqPort).bits.s1 := contiguous_pte_to_merge_ptwResp(resp_pte_sector(llptw_out.bits.id).asUInt, llptw_out.bits.req_info.vpn, llptw_out.bits.af, true, s2xlate = llptw_out.bits.req_info.s2xlate) 474 mergeArb(i).in(outArbMqPort).bits.s2 := llptw_out.bits.h_resp 475 mergeArb(i).out.ready := outArb(i).in(0).ready 476 } 477 478 for (i <- 0 until PtwWidth) { 479 outArb(i).in(0).valid := mergeArb(i).out.valid 480 outArb(i).in(0).bits.s2xlate := mergeArb(i).out.bits.s2xlate 481 outArb(i).in(0).bits.s1 := merge_ptwResp_to_sector_ptwResp(mergeArb(i).out.bits.s1) 482 outArb(i).in(0).bits.s2 := mergeArb(i).out.bits.s2 483 } 484 485 // io.tlb.map(_.resp) <> outArb.map(_.out) 486 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 487 case (resp, out) => resp <> out 488 } 489 490 // sfence 491 when (flush) { 492 for (i <- 0 until MemReqWidth) { 493 when (waiting_resp(i)) { 494 flush_latch(i) := true.B 495 } 496 } 497 } 498 // mem -> control signal 499 // waiting_resp and sfence_latch will be reset when mem_resp_done 500 when (mem_resp_done) { 501 waiting_resp(mem.d.bits.source) := false.B 502 flush_latch(mem.d.bits.source) := false.B 503 } 504 505 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 506 sink.valid := source.valid && !block_signal 507 source.ready := sink.ready && !block_signal 508 sink.bits := source.bits 509 } 510 511 def get_part(data: Vec[UInt], index: UInt): UInt = { 512 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 513 inner_data(index) 514 } 515 516 // not_super means that this is a normal page 517 // valididx(i) will be all true when super page to be convenient for l1 tlb matching 518 def contiguous_pte_to_merge_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean, not_super: Boolean = true, s2xlate: UInt) : PtwMergeResp = { 519 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 520 val ptw_merge_resp = Wire(new PtwMergeResp()) 521 val hasS2xlate = s2xlate =/= noS2xlate 522 for (i <- 0 until tlbcontiguous) { 523 val pte_in = pte(64 * i + 63, 64 * i).asTypeOf(new PteBundle()) 524 val ptw_resp = Wire(new PtwMergeEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true)) 525 ptw_resp.ppn := pte_in.ppn(ppnLen - 1, sectortlbwidth) 526 ptw_resp.ppn_low := pte_in.ppn(sectortlbwidth - 1, 0) 527 ptw_resp.level.map(_ := 2.U) 528 ptw_resp.perm.map(_ := pte_in.getPerm()) 529 ptw_resp.tag := vpn(vpnLen - 1, sectortlbwidth) 530 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 531 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && (af || pte_in.isAf()) 532 ptw_resp.v := !ptw_resp.pf 533 ptw_resp.prefetch := DontCare 534 ptw_resp.asid := Mux(hasS2xlate, vsatp.asid, satp.asid) 535 ptw_resp.vmid.map(_ := hgatp.asid) 536 ptw_merge_resp.entry(i) := ptw_resp 537 } 538 ptw_merge_resp.pteidx := UIntToOH(vpn(sectortlbwidth - 1, 0)).asBools 539 ptw_merge_resp.not_super := not_super.B 540 ptw_merge_resp 541 } 542 543 def merge_ptwResp_to_sector_ptwResp(pte: PtwMergeResp) : PtwSectorResp = { 544 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 545 val ptw_sector_resp = Wire(new PtwSectorResp) 546 ptw_sector_resp.entry.tag := pte.entry(OHToUInt(pte.pteidx)).tag 547 ptw_sector_resp.entry.asid := pte.entry(OHToUInt(pte.pteidx)).asid 548 ptw_sector_resp.entry.vmid.map(_ := pte.entry(OHToUInt(pte.pteidx)).vmid.getOrElse(0.U)) 549 ptw_sector_resp.entry.ppn := pte.entry(OHToUInt(pte.pteidx)).ppn 550 ptw_sector_resp.entry.perm.map(_ := pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle))) 551 ptw_sector_resp.entry.level.map(_ := pte.entry(OHToUInt(pte.pteidx)).level.getOrElse(0.U(2.W))) 552 ptw_sector_resp.entry.prefetch := pte.entry(OHToUInt(pte.pteidx)).prefetch 553 ptw_sector_resp.entry.v := pte.entry(OHToUInt(pte.pteidx)).v 554 ptw_sector_resp.af := pte.entry(OHToUInt(pte.pteidx)).af 555 ptw_sector_resp.pf := pte.entry(OHToUInt(pte.pteidx)).pf 556 ptw_sector_resp.addr_low := OHToUInt(pte.pteidx) 557 ptw_sector_resp.pteidx := pte.pteidx 558 for (i <- 0 until tlbcontiguous) { 559 val ppn_equal = pte.entry(i).ppn === pte.entry(OHToUInt(pte.pteidx)).ppn 560 val perm_equal = pte.entry(i).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt === pte.entry(OHToUInt(pte.pteidx)).perm.getOrElse(0.U.asTypeOf(new PtePermBundle)).asUInt 561 val v_equal = pte.entry(i).v === pte.entry(OHToUInt(pte.pteidx)).v 562 val af_equal = pte.entry(i).af === pte.entry(OHToUInt(pte.pteidx)).af 563 val pf_equal = pte.entry(i).pf === pte.entry(OHToUInt(pte.pteidx)).pf 564 ptw_sector_resp.valididx(i) := (ppn_equal && perm_equal && v_equal && af_equal && pf_equal) || !pte.not_super 565 ptw_sector_resp.ppn_low(i) := pte.entry(i).ppn_low 566 } 567 ptw_sector_resp.valididx(OHToUInt(pte.pteidx)) := true.B 568 ptw_sector_resp 569 } 570 571 def outReady(source: UInt, port: Int): Bool = { 572 MuxLookup(source, true.B)((0 until PtwWidth).map(i => i.U -> mergeArb(i).in(port).ready)) 573 } 574 575 // debug info 576 for (i <- 0 until PtwWidth) { 577 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 578 } 579 XSDebug(p"[sfence] ${io.sfence}\n") 580 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 581 582 for (i <- 0 until PtwWidth) { 583 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire) 584 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 585 } 586 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 587 for (i <- 0 until (MemReqWidth + 1)) { 588 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 589 } 590 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 591 XSPerfAccumulate("mem_count", mem.a.fire) 592 for (i <- 0 until PtwWidth) { 593 XSPerfAccumulate(s"llptw_ppn_af${i}", mergeArb(i).in(outArbMqPort).valid && mergeArb(i).in(outArbMqPort).bits.s1.entry(OHToUInt(mergeArb(i).in(outArbMqPort).bits.s1.pteidx)).af && !llptw_out.bits.af) 594 XSPerfAccumulate(s"access_fault${i}", io.tlb(i).resp.fire && io.tlb(i).resp.bits.s1.af) 595 } 596 597 // print configs 598 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 599 600 // time out assert 601 for (i <- 0 until MemReqWidth) { 602 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 603 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 604 } 605 606 607 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 608 generatePerfEvent() 609 610 val isWriteL1TlbTable = WireInit(Constantin.createRecord("isWriteL1TlbTable" + p(XSCoreParamsKey).HartId.toString)) 611 val L1TlbTable = ChiselDB.createTable("L1Tlb_hart" + p(XSCoreParamsKey).HartId.toString, new L1TlbDB) 612 val ITlbReqDB, DTlbReqDB, ITlbRespDB, DTlbRespDB = Wire(new L1TlbDB) 613 ITlbReqDB.vpn := io.tlb(0).req(0).bits.vpn 614 DTlbReqDB.vpn := io.tlb(1).req(0).bits.vpn 615 ITlbRespDB.vpn := io.tlb(0).resp.bits.s1.entry.tag 616 DTlbRespDB.vpn := io.tlb(1).resp.bits.s1.entry.tag 617 L1TlbTable.log(ITlbReqDB, isWriteL1TlbTable.orR && io.tlb(0).req(0).fire, "ITlbReq", clock, reset) 618 L1TlbTable.log(DTlbReqDB, isWriteL1TlbTable.orR && io.tlb(1).req(0).fire, "DTlbReq", clock, reset) 619 L1TlbTable.log(ITlbRespDB, isWriteL1TlbTable.orR && io.tlb(0).resp.fire, "ITlbResp", clock, reset) 620 L1TlbTable.log(DTlbRespDB, isWriteL1TlbTable.orR && io.tlb(1).resp.fire, "DTlbResp", clock, reset) 621 622 val isWritePageCacheTable = WireInit(Constantin.createRecord("isWritePageCacheTable" + p(XSCoreParamsKey).HartId.toString)) 623 val PageCacheTable = ChiselDB.createTable("PageCache_hart" + p(XSCoreParamsKey).HartId.toString, new PageCacheDB) 624 val PageCacheDB = Wire(new PageCacheDB) 625 PageCacheDB.vpn := Cat(cache.io.resp.bits.toTlb.entry(0).tag, OHToUInt(cache.io.resp.bits.toTlb.pteidx)) 626 PageCacheDB.source := cache.io.resp.bits.req_info.source 627 PageCacheDB.bypassed := cache.io.resp.bits.bypassed 628 PageCacheDB.is_first := cache.io.resp.bits.isFirst 629 PageCacheDB.prefetched := cache.io.resp.bits.toTlb.entry(0).prefetch 630 PageCacheDB.prefetch := cache.io.resp.bits.prefetch 631 PageCacheDB.l2Hit := cache.io.resp.bits.toFsm.l2Hit 632 PageCacheDB.l1Hit := cache.io.resp.bits.toFsm.l1Hit 633 PageCacheDB.hit := cache.io.resp.bits.hit 634 PageCacheTable.log(PageCacheDB, isWritePageCacheTable.orR && cache.io.resp.fire, "PageCache", clock, reset) 635 636 val isWritePTWTable = WireInit(Constantin.createRecord("isWritePTWTable" + p(XSCoreParamsKey).HartId.toString)) 637 val PTWTable = ChiselDB.createTable("PTW_hart" + p(XSCoreParamsKey).HartId.toString, new PTWDB) 638 val PTWReqDB, PTWRespDB, LLPTWReqDB, LLPTWRespDB = Wire(new PTWDB) 639 PTWReqDB.vpn := ptw.io.req.bits.req_info.vpn 640 PTWReqDB.source := ptw.io.req.bits.req_info.source 641 PTWRespDB.vpn := ptw.io.refill.req_info.vpn 642 PTWRespDB.source := ptw.io.refill.req_info.source 643 LLPTWReqDB.vpn := llptw.io.in.bits.req_info.vpn 644 LLPTWReqDB.source := llptw.io.in.bits.req_info.source 645 LLPTWRespDB.vpn := llptw.io.mem.refill.vpn 646 LLPTWRespDB.source := llptw.io.mem.refill.source 647 PTWTable.log(PTWReqDB, isWritePTWTable.orR && ptw.io.req.fire, "PTWReq", clock, reset) 648 PTWTable.log(PTWRespDB, isWritePTWTable.orR && ptw.io.mem.resp.fire, "PTWResp", clock, reset) 649 PTWTable.log(LLPTWReqDB, isWritePTWTable.orR && llptw.io.in.fire, "LLPTWReq", clock, reset) 650 PTWTable.log(LLPTWRespDB, isWritePTWTable.orR && llptw.io.mem.resp.fire, "LLPTWResp", clock, reset) 651 652 val isWriteL2TlbMissQueueTable = WireInit(Constantin.createRecord("isWriteL2TlbMissQueueTable" + p(XSCoreParamsKey).HartId.toString)) 653 val L2TlbMissQueueTable = ChiselDB.createTable("L2TlbMissQueue_hart" + p(XSCoreParamsKey).HartId.toString, new L2TlbMissQueueDB) 654 val L2TlbMissQueueInDB, L2TlbMissQueueOutDB = Wire(new L2TlbMissQueueDB) 655 L2TlbMissQueueInDB.vpn := missQueue.io.in.bits.vpn 656 L2TlbMissQueueOutDB.vpn := missQueue.io.out.bits.vpn 657 L2TlbMissQueueTable.log(L2TlbMissQueueInDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.in.fire, "L2TlbMissQueueIn", clock, reset) 658 L2TlbMissQueueTable.log(L2TlbMissQueueOutDB, isWriteL2TlbMissQueueTable.orR && missQueue.io.out.fire, "L2TlbMissQueueOut", clock, reset) 659} 660 661/** BlockHelper, block missqueue, not to send too many req to cache 662 * Parameter: 663 * enable: enable BlockHelper, mq should not send too many reqs 664 * start: when miss queue out fire and need, block miss queue's out 665 * block: block miss queue's out 666 * latency: last missqueue out's cache access latency 667 */ 668class BlockHelper(latency: Int)(implicit p: Parameters) extends XSModule { 669 val io = IO(new Bundle { 670 val enable = Input(Bool()) 671 val start = Input(Bool()) 672 val block = Output(Bool()) 673 }) 674 675 val count = RegInit(0.U(log2Ceil(latency).W)) 676 val valid = RegInit(false.B) 677 val work = RegInit(true.B) 678 679 io.block := valid 680 681 when (io.start && work) { valid := true.B } 682 when (valid) { count := count + 1.U } 683 when (count === (latency.U) || io.enable) { 684 valid := false.B 685 work := io.enable 686 count := 0.U 687 } 688} 689 690class PTEHelper() extends ExtModule { 691 val clock = IO(Input(Clock())) 692 val enable = IO(Input(Bool())) 693 val satp = IO(Input(UInt(64.W))) 694 val vpn = IO(Input(UInt(64.W))) 695 val pte = IO(Output(UInt(64.W))) 696 val level = IO(Output(UInt(8.W))) 697 val pf = IO(Output(UInt(8.W))) 698} 699 700class PTWDelayN[T <: Data](gen: T, n: Int, flush: Bool) extends Module { 701 val io = IO(new Bundle() { 702 val in = Input(gen) 703 val out = Output(gen) 704 val ptwflush = Input(flush.cloneType) 705 }) 706 val out = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 707 val t = RegInit(VecInit(Seq.fill(n)(0.U.asTypeOf(gen)))) 708 out(0) := io.in 709 if (n == 1) { 710 io.out := out(0) 711 } else { 712 when (io.ptwflush) { 713 for (i <- 0 until n) { 714 t(i) := 0.U.asTypeOf(gen) 715 out(i) := 0.U.asTypeOf(gen) 716 } 717 io.out := 0.U.asTypeOf(gen) 718 } .otherwise { 719 for (i <- 1 until n) { 720 t(i-1) := out(i-1) 721 out(i) := t(i-1) 722 } 723 io.out := out(n-1) 724 } 725 } 726} 727 728object PTWDelayN { 729 def apply[T <: Data](in: T, n: Int, flush: Bool): T = { 730 val delay = Module(new PTWDelayN(in.cloneType, n, flush)) 731 delay.io.in := in 732 delay.io.ptwflush := flush 733 delay.io.out 734 } 735} 736 737class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 738 val io = IO(new L2TLBIO) 739 val flush = VecInit(Seq.fill(PtwWidth)(false.B)) 740 flush(0) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, itlbParams.fenceDelay) 741 flush(1) := DelayN(io.sfence.valid || io.csr.tlb.satp.changed, ldtlbParams.fenceDelay) 742 for (i <- 0 until PtwWidth) { 743 val helper = Module(new PTEHelper()) 744 helper.clock := clock 745 helper.satp := io.csr.tlb.satp.ppn 746 747 if (coreParams.softPTWDelay == 1) { 748 helper.enable := io.tlb(i).req(0).fire 749 helper.vpn := io.tlb(i).req(0).bits.vpn 750 } else { 751 helper.enable := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay - 1, flush(i)) 752 helper.vpn := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay - 1, flush(i)) 753 } 754 755 val pte = helper.pte.asTypeOf(new PteBundle) 756 val level = helper.level 757 val pf = helper.pf 758 val empty = RegInit(true.B) 759 when (io.tlb(i).req(0).fire) { 760 empty := false.B 761 } .elsewhen (io.tlb(i).resp.fire || flush(i)) { 762 empty := true.B 763 } 764 765 io.tlb(i).req(0).ready := empty || io.tlb(i).resp.fire 766 io.tlb(i).resp.valid := PTWDelayN(io.tlb(i).req(0).fire, coreParams.softPTWDelay, flush(i)) 767 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 768 io.tlb(i).resp.bits.s1.entry.tag := PTWDelayN(io.tlb(i).req(0).bits.vpn, coreParams.softPTWDelay, flush(i)) 769 io.tlb(i).resp.bits.s1.entry.ppn := pte.ppn 770 io.tlb(i).resp.bits.s1.entry.perm.map(_ := pte.getPerm()) 771 io.tlb(i).resp.bits.s1.entry.level.map(_ := level) 772 io.tlb(i).resp.bits.s1.pf := pf 773 io.tlb(i).resp.bits.s1.af := DontCare // TODO: implement it 774 io.tlb(i).resp.bits.s1.entry.v := !pf 775 io.tlb(i).resp.bits.s1.entry.prefetch := DontCare 776 io.tlb(i).resp.bits.s1.entry.asid := io.csr.tlb.satp.asid 777 } 778} 779 780class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 781 override def shouldBeInlined: Boolean = false 782 val useSoftPTW = coreParams.softPTW 783 val node = if (!useSoftPTW) TLIdentityNode() else null 784 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 785 if (!useSoftPTW) { 786 node := ptw.node 787 } 788 789 class L2TLBWrapperImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) with HasPerfEvents { 790 val io = IO(new L2TLBIO) 791 val perfEvents = if (useSoftPTW) { 792 val fake_ptw = Module(new FakePTW()) 793 io <> fake_ptw.io 794 Seq() 795 } 796 else { 797 io <> ptw.module.io 798 ptw.module.getPerfEvents 799 } 800 generatePerfEvent() 801 } 802 803 lazy val module = new L2TLBWrapperImp(this) 804} 805