1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.experimental.ExtModule 22import chisel3.util._ 23import chisel3.internal.naming.chiselName 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29import xiangshan.backend.fu.{PMP, PMPChecker, PMPReqBundle, PMPRespBundle} 30import xiangshan.backend.fu.util.HasCSRConst 31 32class L2TLB()(implicit p: Parameters) extends LazyModule with HasPtwConst { 33 34 val node = TLClientNode(Seq(TLMasterPortParameters.v1( 35 clients = Seq(TLMasterParameters.v1( 36 "ptw", 37 sourceId = IdRange(0, MemReqWidth) 38 )) 39 ))) 40 41 lazy val module = new L2TLBImp(this) 42} 43 44@chiselName 45class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) with HasCSRConst with HasPerfEvents { 46 47 val (mem, edge) = outer.node.out.head 48 49 val io = IO(new L2TLBIO) 50 val difftestIO = IO(new Bundle() { 51 val ptwResp = Output(Bool()) 52 val ptwAddr = Output(UInt(64.W)) 53 val ptwData = Output(Vec(4, UInt(64.W))) 54 }) 55 56 /* Ptw processes multiple requests 57 * Divide Ptw procedure into two stages: cache access ; mem access if cache miss 58 * miss queue itlb dtlb 59 * | | | 60 * ------arbiter------ 61 * | 62 * l1 - l2 - l3 - sp 63 * | 64 * ------------------------------------------- 65 * miss | queue | hit 66 * [][][][][][] | 67 * | | 68 * state machine accessing mem | 69 * | | 70 * ---------------arbiter--------------------- 71 * | | 72 * itlb dtlb 73 */ 74 75 difftestIO <> DontCare 76 77 val sfence = DelayN(io.sfence, 2) 78 val csr = DelayN(io.csr.tlb, 2) 79 val satp = csr.satp 80 val priv = csr.priv 81 val flush = sfence.valid || csr.satp.changed 82 83 val pmp = Module(new PMP()) 84 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(lgMaxSize = 3, sameCycle = true)).io)) 85 pmp.io.distribute_csr := io.csr.distribute_csr 86 pmp_check.foreach(_.check_env.apply(ModeS, pmp.io.pmp, pmp.io.pma)) 87 88 val missQueue = Module(new L2TlbMissQueue) 89 val cache = Module(new PtwCache) 90 val ptw = Module(new PTW) 91 val llptw = Module(new LLPTW) 92 val arb1 = Module(new Arbiter(new PtwReq, PtwWidth)) 93 val arb2 = Module(new Arbiter(new Bundle { 94 val vpn = UInt(vpnLen.W) 95 val source = UInt(bSourceWidth.W) 96 }, if (l2tlbParams.enablePrefetch) 3 else 2)) 97 val outArb = (0 until PtwWidth).map(i => Module(new Arbiter(new PtwResp, 3)).io) 98 val outArbCachePort = 0 99 val outArbFsmPort = 1 100 val outArbMqPort = 2 101 102 // NOTE: when cache out but miss and ptw doesnt accept, 103 arb1.io.in <> VecInit(io.tlb.map(_.req(0))) 104 arb1.io.out.ready := arb2.io.in(1).ready 105 106 val InArbMissQueuePort = 0 107 val InArbTlbPort = 1 108 val InArbPrefetchPort = 2 109 block_decoupled(missQueue.io.out, arb2.io.in(InArbMissQueuePort), !ptw.io.req.ready) 110 arb2.io.in(InArbTlbPort).valid := arb1.io.out.valid 111 arb2.io.in(InArbTlbPort).bits.vpn := arb1.io.out.bits.vpn 112 arb2.io.in(InArbTlbPort).bits.source := arb1.io.chosen 113 if (l2tlbParams.enablePrefetch) { 114 val prefetch = Module(new L2TlbPrefetch()) 115 val recv = cache.io.resp 116 // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch 117 // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch 118 prefetch.io.in.valid := recv.fire() && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit || 119 recv.bits.prefetch) && recv.bits.isFirst 120 prefetch.io.in.bits.vpn := recv.bits.req_info.vpn 121 prefetch.io.sfence := sfence 122 prefetch.io.csr := csr 123 arb2.io.in(InArbPrefetchPort) <> prefetch.io.out 124 } 125 arb2.io.out.ready := cache.io.req.ready 126 127 val LLPTWARB_CACHE=0 128 val LLPTWARB_PTW=1 129 val llptw_arb = Module(new Arbiter(new LLPTWInBundle, 2)) 130 llptw_arb.io.in(LLPTWARB_CACHE).valid := cache.io.resp.valid && !cache.io.resp.bits.hit && cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed 131 llptw_arb.io.in(LLPTWARB_CACHE).bits.req_info := cache.io.resp.bits.req_info 132 llptw_arb.io.in(LLPTWARB_CACHE).bits.ppn := cache.io.resp.bits.toFsm.ppn 133 llptw_arb.io.in(LLPTWARB_PTW) <> ptw.io.llptw 134 llptw.io.in <> llptw_arb.io.out 135 llptw.io.sfence := sfence 136 llptw.io.csr := csr 137 138 cache.io.req.valid := arb2.io.out.valid 139 cache.io.req.bits.req_info.vpn := arb2.io.out.bits.vpn 140 cache.io.req.bits.req_info.source := arb2.io.out.bits.source 141 cache.io.req.bits.isFirst := arb2.io.chosen =/= InArbMissQueuePort.U 142 cache.io.req.bits.bypassed.map(_ := false.B) 143 cache.io.sfence := sfence 144 cache.io.csr := csr 145 cache.io.resp.ready := Mux(cache.io.resp.bits.hit, 146 outReady(cache.io.resp.bits.req_info.source, outArbCachePort), 147 Mux(cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed, llptw_arb.io.in(LLPTWARB_CACHE).ready, 148 Mux(cache.io.resp.bits.bypassed, missQueue.io.in.ready, missQueue.io.in.ready || ptw.io.req.ready))) 149 150 missQueue.io.in.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && 151 (!cache.io.resp.bits.toFsm.l2Hit || cache.io.resp.bits.bypassed) && 152 !from_pre(cache.io.resp.bits.req_info.source) && 153 (cache.io.resp.bits.bypassed || !ptw.io.req.ready) 154 missQueue.io.in.bits := cache.io.resp.bits.req_info 155 missQueue.io.sfence := sfence 156 missQueue.io.csr := csr 157 158 // NOTE: missQueue req has higher priority 159 ptw.io.req.valid := cache.io.resp.valid && !cache.io.resp.bits.hit && !cache.io.resp.bits.toFsm.l2Hit && !cache.io.resp.bits.bypassed 160 ptw.io.req.bits.req_info := cache.io.resp.bits.req_info 161 ptw.io.req.bits.l1Hit := cache.io.resp.bits.toFsm.l1Hit 162 ptw.io.req.bits.ppn := cache.io.resp.bits.toFsm.ppn 163 ptw.io.csr := csr 164 ptw.io.sfence := sfence 165 ptw.io.resp.ready := outReady(ptw.io.resp.bits.source, outArbFsmPort) 166 167 // mem req 168 def blockBytes_align(addr: UInt) = { 169 Cat(addr(PAddrBits - 1, log2Up(l2tlbParams.blockBytes)), 0.U(log2Up(l2tlbParams.blockBytes).W)) 170 } 171 def addr_low_from_vpn(vpn: UInt) = { 172 vpn(log2Ceil(l2tlbParams.blockBytes)-log2Ceil(XLEN/8)-1, 0) 173 } 174 def addr_low_from_paddr(paddr: UInt) = { 175 paddr(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 176 } 177 def from_missqueue(id: UInt) = { 178 (id =/= l2tlbParams.llptwsize.U) 179 } 180 val waiting_resp = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 181 val flush_latch = RegInit(VecInit(Seq.fill(MemReqWidth)(false.B))) 182 for (i <- waiting_resp.indices) { 183 assert(!flush_latch(i) || waiting_resp(i)) // when sfence_latch wait for mem resp, waiting_resp should be true 184 } 185 186 val llptw_out = llptw.io.out 187 val llptw_mem = llptw.io.mem 188 llptw_mem.req_mask := waiting_resp.take(l2tlbParams.llptwsize) 189 ptw.io.mem.mask := waiting_resp.last 190 191 val mem_arb = Module(new Arbiter(new L2TlbMemReqBundle(), 2)) 192 mem_arb.io.in(0) <> ptw.io.mem.req 193 mem_arb.io.in(1) <> llptw_mem.req 194 mem_arb.io.out.ready := mem.a.ready && !flush 195 196 // assert, should not send mem access at same addr for twice. 197 val last_resp_vpn = RegEnable(cache.io.refill.bits.req_info.vpn, cache.io.refill.valid) 198 val last_resp_level = RegEnable(cache.io.refill.bits.level, cache.io.refill.valid) 199 val last_resp_v = RegInit(false.B) 200 val last_has_invalid = !Cat(cache.io.refill.bits.ptes.asTypeOf(Vec(blockBits/XLEN, UInt(XLEN.W))).map(a => a(0))).andR 201 when (cache.io.refill.valid) { last_resp_v := !last_has_invalid} 202 when (flush) { last_resp_v := false.B } 203 XSError(last_resp_v && cache.io.refill.valid && 204 (cache.io.refill.bits.req_info.vpn === last_resp_vpn) && 205 (cache.io.refill.bits.level === last_resp_level), 206 "l2tlb should not access mem at same addr for twice") 207 // ATTENTION: this may wronngly assert when: a ptes is l2, last part is valid, 208 // but the current part is invalid, so one more mem access happened 209 // If this happened, remove the assert. 210 211 val req_addr_low = Reg(Vec(MemReqWidth, UInt((log2Up(l2tlbParams.blockBytes)-log2Up(XLEN/8)).W))) 212 213 when (llptw.io.in.fire()) { 214 // when enq miss queue, set the req_addr_low to receive the mem resp data part 215 req_addr_low(llptw_mem.enq_ptr) := addr_low_from_vpn(llptw.io.in.bits.req_info.vpn) 216 } 217 when (mem_arb.io.out.fire()) { 218 req_addr_low(mem_arb.io.out.bits.id) := addr_low_from_paddr(mem_arb.io.out.bits.addr) 219 waiting_resp(mem_arb.io.out.bits.id) := true.B 220 } 221 // mem read 222 val memRead = edge.Get( 223 fromSource = mem_arb.io.out.bits.id, 224 // toAddress = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0), 225 toAddress = blockBytes_align(mem_arb.io.out.bits.addr), 226 lgSize = log2Up(l2tlbParams.blockBytes).U 227 )._2 228 mem.a.bits := memRead 229 mem.a.valid := mem_arb.io.out.valid && !flush 230 mem.d.ready := true.B 231 // mem -> data buffer 232 val refill_data = Reg(Vec(blockBits / l1BusDataWidth, UInt(l1BusDataWidth.W))) 233 val refill_helper = edge.firstlastHelper(mem.d.bits, mem.d.fire()) 234 val mem_resp_done = refill_helper._3 235 val mem_resp_from_mq = from_missqueue(mem.d.bits.source) 236 when (mem.d.valid) { 237 assert(mem.d.bits.source <= l2tlbParams.llptwsize.U) 238 refill_data(refill_helper._4) := mem.d.bits.data 239 } 240 // save only one pte for each id 241 // (miss queue may can't resp to tlb with low latency, it should have highest priority, but diffcult to design cache) 242 val resp_pte = VecInit((0 until MemReqWidth).map(i => 243 if (i == l2tlbParams.llptwsize) {DataHoldBypass(get_part(refill_data, req_addr_low(i)), RegNext(mem_resp_done && !mem_resp_from_mq)) } 244 else { DataHoldBypass(get_part(refill_data, req_addr_low(i)), llptw_mem.buffer_it(i)) } 245 )) 246 247 // mem -> miss queue 248 llptw_mem.resp.valid := mem_resp_done && mem_resp_from_mq 249 llptw_mem.resp.bits.id := mem.d.bits.source 250 // mem -> ptw 251 ptw.io.mem.req.ready := mem.a.ready 252 ptw.io.mem.resp.valid := mem_resp_done && !mem_resp_from_mq 253 ptw.io.mem.resp.bits := resp_pte.last 254 // mem -> cache 255 val refill_from_mq = RegNext(mem_resp_from_mq) 256 cache.io.refill.valid := RegNext(mem_resp_done && !flush && !flush_latch(mem.d.bits.source)) 257 cache.io.refill.bits.ptes := refill_data.asUInt 258 cache.io.refill.bits.req_info := Mux(refill_from_mq, llptw_mem.refill, ptw.io.refill.req_info) 259 cache.io.refill.bits.level := Mux(refill_from_mq, 2.U, RegEnable(ptw.io.refill.level, 0.U, ptw.io.mem.req.fire())) 260 cache.io.refill.bits.addr_low := RegNext(req_addr_low(mem.d.bits.source)) 261 262 // pmp 263 pmp_check(0).req <> ptw.io.pmp.req 264 ptw.io.pmp.resp <> pmp_check(0).resp 265 pmp_check(1).req <> llptw.io.pmp.req 266 llptw.io.pmp.resp <> pmp_check(1).resp 267 268 llptw_out.ready := outReady(llptw_out.bits.req_info.source, outArbMqPort) 269 for (i <- 0 until PtwWidth) { 270 outArb(i).in(outArbCachePort).valid := cache.io.resp.valid && cache.io.resp.bits.hit && cache.io.resp.bits.req_info.source===i.U 271 outArb(i).in(outArbCachePort).bits.entry := cache.io.resp.bits.toTlb 272 outArb(i).in(outArbCachePort).bits.pf := !cache.io.resp.bits.toTlb.v 273 outArb(i).in(outArbCachePort).bits.af := false.B 274 outArb(i).in(outArbFsmPort).valid := ptw.io.resp.valid && ptw.io.resp.bits.source===i.U 275 outArb(i).in(outArbFsmPort).bits := ptw.io.resp.bits.resp 276 outArb(i).in(outArbMqPort).valid := llptw_out.valid && llptw_out.bits.req_info.source===i.U 277 outArb(i).in(outArbMqPort).bits := pte_to_ptwResp(resp_pte(llptw_out.bits.id), llptw_out.bits.req_info.vpn, llptw_out.bits.af, true) 278 } 279 280 // io.tlb.map(_.resp) <> outArb.map(_.out) 281 io.tlb.map(_.resp).zip(outArb.map(_.out)).map{ 282 case (resp, out) => resp <> out 283 } 284 285 // sfence 286 when (flush) { 287 for (i <- 0 until MemReqWidth) { 288 when (waiting_resp(i)) { 289 flush_latch(i) := true.B 290 } 291 } 292 } 293 // mem -> control signal 294 // waiting_resp and sfence_latch will be reset when mem_resp_done 295 when (mem_resp_done) { 296 waiting_resp(mem.d.bits.source) := false.B 297 flush_latch(mem.d.bits.source) := false.B 298 } 299 300 def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = { 301 sink.valid := source.valid && !block_signal 302 source.ready := sink.ready && !block_signal 303 sink.bits := source.bits 304 } 305 306 def get_part(data: Vec[UInt], index: UInt): UInt = { 307 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 308 inner_data(index) 309 } 310 311 def pte_to_ptwResp(pte: UInt, vpn: UInt, af: Bool, af_first: Boolean) : PtwResp = { 312 val pte_in = pte.asTypeOf(new PteBundle()) 313 val ptw_resp = Wire(new PtwResp()) 314 ptw_resp.entry.ppn := pte_in.ppn 315 ptw_resp.entry.level.map(_ := 2.U) 316 ptw_resp.entry.perm.map(_ := pte_in.getPerm()) 317 ptw_resp.entry.tag := vpn 318 ptw_resp.pf := (if (af_first) !af else true.B) && pte_in.isPf(2.U) 319 ptw_resp.af := (if (!af_first) pte_in.isPf(2.U) else true.B) && af 320 ptw_resp.entry.v := !ptw_resp.pf 321 ptw_resp.entry.prefetch := DontCare 322 ptw_resp.entry.asid := satp.asid 323 ptw_resp 324 } 325 326 def outReady(source: UInt, port: Int): Bool = { 327 MuxLookup(source, true.B, 328 (0 until PtwWidth).map(i => i.U -> outArb(i).in(port).ready)) 329 } 330 331 // debug info 332 for (i <- 0 until PtwWidth) { 333 XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n") 334 } 335 XSDebug(p"[sfence] ${sfence}\n") 336 XSDebug(p"[io.csr.tlb] ${io.csr.tlb}\n") 337 338 for (i <- 0 until PtwWidth) { 339 XSPerfAccumulate(s"req_count${i}", io.tlb(i).req(0).fire()) 340 XSPerfAccumulate(s"req_blocked_count_${i}", io.tlb(i).req(0).valid && !io.tlb(i).req(0).ready) 341 } 342 XSPerfAccumulate(s"req_blocked_by_mq", arb1.io.out.valid && missQueue.io.out.valid) 343 for (i <- 0 until (MemReqWidth + 1)) { 344 XSPerfAccumulate(s"mem_req_util${i}", PopCount(waiting_resp) === i.U) 345 } 346 XSPerfAccumulate("mem_cycle", PopCount(waiting_resp) =/= 0.U) 347 XSPerfAccumulate("mem_count", mem.a.fire()) 348 349 // print configs 350 println(s"${l2tlbParams.name}: a ptw, a llptw with size ${l2tlbParams.llptwsize}, miss queue size ${MissQueueSize} l1:${l2tlbParams.l1Size} fa l2: nSets ${l2tlbParams.l2nSets} nWays ${l2tlbParams.l2nWays} l3: ${l2tlbParams.l3nSets} nWays ${l2tlbParams.l3nWays} blockBytes:${l2tlbParams.blockBytes}") 351 352 // time out assert 353 for (i <- 0 until MemReqWidth) { 354 TimeOutAssert(waiting_resp(i), timeOutThreshold, s"ptw mem resp time out wait_resp${i}") 355 TimeOutAssert(flush_latch(i), timeOutThreshold, s"ptw mem resp time out flush_latch${i}") 356 } 357 358 359 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) 360 generatePerfEvent() 361} 362 363class PTEHelper() extends ExtModule { 364 val clock = IO(Input(Clock())) 365 val enable = IO(Input(Bool())) 366 val satp = IO(Input(UInt(64.W))) 367 val vpn = IO(Input(UInt(64.W))) 368 val pte = IO(Output(UInt(64.W))) 369 val level = IO(Output(UInt(8.W))) 370 val pf = IO(Output(UInt(8.W))) 371} 372 373class FakePTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 374 val io = IO(new L2TLBIO) 375 376 for (i <- 0 until PtwWidth) { 377 io.tlb(i).req(0).ready := true.B 378 379 val helper = Module(new PTEHelper()) 380 helper.clock := clock 381 helper.enable := io.tlb(i).req(0).valid 382 helper.satp := io.csr.tlb.satp.ppn 383 helper.vpn := io.tlb(i).req(0).bits.vpn 384 val pte = helper.pte.asTypeOf(new PteBundle) 385 val level = helper.level 386 val pf = helper.pf 387 388 io.tlb(i).resp.valid := RegNext(io.tlb(i).req(0).valid) 389 assert(!io.tlb(i).resp.valid || io.tlb(i).resp.ready) 390 io.tlb(i).resp.bits.entry.tag := RegNext(io.tlb(i).req(0).bits.vpn) 391 io.tlb(i).resp.bits.entry.ppn := pte.ppn 392 io.tlb(i).resp.bits.entry.perm.map(_ := pte.getPerm()) 393 io.tlb(i).resp.bits.entry.level.map(_ := level) 394 io.tlb(i).resp.bits.pf := pf 395 io.tlb(i).resp.bits.af := DontCare // TODO: implement it 396 } 397} 398 399class L2TLBWrapper()(implicit p: Parameters) extends LazyModule with HasXSParameter { 400 val useSoftPTW = coreParams.softPTW 401 val node = if (!useSoftPTW) TLIdentityNode() else null 402 val ptw = if (!useSoftPTW) LazyModule(new L2TLB()) else null 403 if (!useSoftPTW) { 404 node := ptw.node 405 } 406 407 lazy val module = new LazyModuleImp(this) with HasPerfEvents { 408 val io = IO(new L2TLBIO) 409 val perfEvents = if (useSoftPTW) { 410 val fake_ptw = Module(new FakePTW()) 411 io <> fake_ptw.io 412 Seq() 413 } 414 else { 415 io <> ptw.module.io 416 ptw.module.getPerfEvents 417 } 418 generatePerfEvent() 419 } 420} 421