1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientMetadata 23import utils.{HasPerfEvents, XSDebug, XSPerfAccumulate} 24import xiangshan.L1CacheErrorInfo 25 26class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPerfEvents { 27 val io = IO(new DCacheBundle { 28 // incoming requests 29 val lsu = Flipped(new DCacheLoadIO) 30 // req got nacked in stage 0? 31 val nack = Input(Bool()) 32 33 // meta and data array read port 34 val meta_read = DecoupledIO(new MetaReadReq) 35 val meta_resp = Input(Vec(nWays, new Meta)) 36 val error_flag_resp = Input(Vec(nWays, Bool())) 37 38 val tag_read = DecoupledIO(new TagReadReq) 39 val tag_resp = Input(Vec(nWays, UInt(encTagBits.W))) 40 41 val banked_data_read = DecoupledIO(new L1BankedDataReadReq) 42 val banked_data_resp = Input(Vec(DCacheBanks, new L1BankedDataReadResult())) 43 val read_error_delayed = Input(Bool()) 44 45 // banked data read conflict 46 val bank_conflict_slow = Input(Bool()) 47 val bank_conflict_fast = Input(Bool()) 48 49 // send miss request to miss queue 50 val miss_req = DecoupledIO(new MissReq) 51 52 // update state vec in replacement algo 53 val replace_access = ValidIO(new ReplacementAccessBundle) 54 // find the way to be replaced 55 val replace_way = new ReplacementWayReqIO 56 57 // load fast wakeup should be disabled when data read is not ready 58 val disable_ld_fast_wakeup = Input(Bool()) 59 60 // ecc error 61 val error = Output(new L1CacheErrorInfo()) 62 }) 63 64 assert(RegNext(io.meta_read.ready)) 65 66 val s1_ready = Wire(Bool()) 67 val s2_ready = Wire(Bool()) 68 // LSU requests 69 // it you got nacked, you can directly passdown 70 val not_nacked_ready = io.meta_read.ready && io.tag_read.ready && s1_ready 71 val nacked_ready = true.B 72 73 // ready can wait for valid 74 io.lsu.req.ready := (!io.nack && not_nacked_ready) || (io.nack && nacked_ready) 75 io.meta_read.valid := io.lsu.req.fire() && !io.nack 76 io.tag_read.valid := io.lsu.req.fire() && !io.nack 77 78 val meta_read = io.meta_read.bits 79 val tag_read = io.tag_read.bits 80 81 // Tag read for new requests 82 meta_read.idx := get_idx(io.lsu.req.bits.addr) 83 meta_read.way_en := ~0.U(nWays.W) 84 // meta_read.tag := DontCare 85 86 tag_read.idx := get_idx(io.lsu.req.bits.addr) 87 tag_read.way_en := ~0.U(nWays.W) 88 89 // Pipeline 90 // -------------------------------------------------------------------------------- 91 // stage 0 92 // -------------------------------------------------------------------------------- 93 // read tag 94 95 val s0_valid = io.lsu.req.fire() 96 val s0_req = io.lsu.req.bits 97 val s0_fire = s0_valid && s1_ready 98 99 assert(RegNext(!(s0_valid && (s0_req.cmd =/= MemoryOpConstants.M_XRD && s0_req.cmd =/= MemoryOpConstants.M_PFR && s0_req.cmd =/= MemoryOpConstants.M_PFW))), "LoadPipe only accepts load req / softprefetch read or write!") 100 dump_pipeline_reqs("LoadPipe s0", s0_valid, s0_req) 101 102 // -------------------------------------------------------------------------------- 103 // stage 1 104 // -------------------------------------------------------------------------------- 105 // tag match, read data 106 107 val s1_valid = RegInit(false.B) 108 val s1_req = RegEnable(s0_req, s0_fire) 109 // in stage 1, load unit gets the physical address 110 val s1_paddr_dup_lsu = io.lsu.s1_paddr_dup_lsu 111 val s1_paddr_dup_dcache = io.lsu.s1_paddr_dup_dcache 112 // LSU may update the address from io.lsu.s1_paddr, which affects the bank read enable only. 113 val s1_vaddr = Cat(s1_req.addr(PAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) 114 val s1_bank_oh = UIntToOH(addr_to_dcache_bank(s1_vaddr)) 115 val s1_nack = RegNext(io.nack) 116 val s1_nack_data = !io.banked_data_read.ready 117 val s1_fire = s1_valid && s2_ready 118 s1_ready := !s1_valid || s1_fire 119 120 when (s0_fire) { s1_valid := true.B } 121 .elsewhen (s1_fire) { s1_valid := false.B } 122 123 dump_pipeline_reqs("LoadPipe s1", s1_valid, s1_req) 124 125 // tag check 126 val meta_resp = io.meta_resp 127 val tag_resp = io.tag_resp.map(r => r(tagBits - 1, 0)) 128 def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) 129 130 // dcache side tag match 131 val s1_tag_eq_way = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_dcache))).asUInt 132 val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta_resp(w).coh.isValid()).asUInt 133 val s1_tag_match = s1_tag_match_way.orR 134 assert(RegNext(!s1_valid || PopCount(s1_tag_match_way) <= 1.U), "tag should not match with more than 1 way") 135 136 val s1_fake_meta = Wire(new Meta) 137// s1_fake_meta.tag := get_tag(s1_paddr_dup_dcache) 138 s1_fake_meta.coh := ClientMetadata.onReset 139 val s1_fake_tag = get_tag(s1_paddr_dup_dcache) 140 141 // when there are no tag match, we give it a Fake Meta 142 // this simplifies our logic in s2 stage 143 val s1_hit_meta = Mux(s1_tag_match, Mux1H(s1_tag_match_way, wayMap((w: Int) => meta_resp(w))), s1_fake_meta) 144 val s1_hit_coh = s1_hit_meta.coh 145 val s1_hit_error = Mux(s1_tag_match, Mux1H(s1_tag_match_way, wayMap((w: Int) => io.error_flag_resp(w))), false.B) 146 147 io.replace_way.set.valid := RegNext(s0_fire) 148 io.replace_way.set.bits := get_idx(s1_vaddr) 149 val s1_repl_way_en = UIntToOH(io.replace_way.way) 150 val s1_repl_tag = Mux1H(s1_repl_way_en, wayMap(w => tag_resp(w))) 151 val s1_repl_coh = Mux1H(s1_repl_way_en, wayMap(w => meta_resp(w).coh)) 152 153 val s1_need_replacement = !s1_tag_match 154 val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way) 155 val s1_coh = Mux(s1_need_replacement, s1_repl_coh, s1_hit_coh) 156 val s1_tag = Mux(s1_need_replacement, s1_repl_tag, get_tag(s1_paddr_dup_dcache)) 157 158 // data read 159 io.banked_data_read.valid := s1_fire && !s1_nack 160 io.banked_data_read.bits.addr := s1_vaddr 161 io.banked_data_read.bits.way_en := s1_tag_match_way 162 163 // get s1_will_send_miss_req in lpad_s1 164 val s1_has_permission = s1_hit_coh.onAccess(s1_req.cmd)._1 165 val s1_new_hit_coh = s1_hit_coh.onAccess(s1_req.cmd)._3 166 val s1_hit = s1_tag_match && s1_has_permission && s1_hit_coh === s1_new_hit_coh 167 val s1_will_send_miss_req = s1_valid && !s1_nack && !s1_nack_data && !s1_hit 168 169 // check ecc error 170 val s1_encTag = Mux1H(s1_tag_match_way, wayMap((w: Int) => io.tag_resp(w))) 171 val s1_flag_error = Mux(s1_need_replacement, false.B, s1_hit_error) // error reported by exist dcache error bit 172 173 // -------------------------------------------------------------------------------- 174 // stage 2 175 // -------------------------------------------------------------------------------- 176 // return data 177 178 // val s2_valid = RegEnable(next = s1_valid && !io.lsu.s1_kill, init = false.B, enable = s1_fire) 179 val s2_valid = RegInit(false.B) 180 val s2_req = RegEnable(s1_req, s1_fire) 181 val s2_paddr = RegEnable(s1_paddr_dup_dcache, s1_fire) 182 val s2_vaddr = RegEnable(s1_vaddr, s1_fire) 183 val s2_bank_oh = RegEnable(s1_bank_oh, s1_fire) 184 s2_ready := true.B 185 186 val s2_fire = s2_valid 187 188 when (s1_fire) { s2_valid := !io.lsu.s1_kill } 189 .elsewhen(io.lsu.resp.fire()) { s2_valid := false.B } 190 191 dump_pipeline_reqs("LoadPipe s2", s2_valid, s2_req) 192 193 // hit, miss, nack, permission checking 194 // dcache side tag match 195 val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_fire) 196 val s2_tag_match = RegEnable(s1_tag_match, s1_fire) 197 198 // lsu side tag match 199 val s2_tag_eq_way_dup_lsu = wayMap((w: Int) => RegNext(tag_resp(w)) === RegNext((get_tag(s1_paddr_dup_lsu)))).asUInt 200 val s2_tag_match_way_dup_lsu = wayMap((w: Int) => s2_tag_eq_way_dup_lsu(w) && RegNext(meta_resp(w).coh.isValid())).asUInt 201 val s2_tag_match_dup_lsu = s2_tag_match_way_dup_lsu.orR 202 val s2_hit_dup_lsu = s2_tag_match_dup_lsu 203 204 io.lsu.s2_hit := s2_hit_dup_lsu 205 206 val s2_hit_meta = RegEnable(s1_hit_meta, s1_fire) 207 val s2_hit_coh = RegEnable(s1_hit_coh, s1_fire) 208 val s2_has_permission = s2_hit_coh.onAccess(s2_req.cmd)._1 // redundant 209 val s2_new_hit_coh = s2_hit_coh.onAccess(s2_req.cmd)._3 // redundant 210 211 val s2_way_en = RegEnable(s1_way_en, s1_fire) 212 val s2_repl_coh = RegEnable(s1_repl_coh, s1_fire) 213 val s2_repl_tag = RegEnable(s1_repl_tag, s1_fire) 214 val s2_encTag = RegEnable(s1_encTag, s1_fire) 215 216 // when req got nacked, upper levels should replay this request 217 // nacked or not 218 val s2_nack_hit = RegEnable(s1_nack, s1_fire) 219 // can no allocate mshr for load miss 220 val s2_nack_no_mshr = io.miss_req.valid && !io.miss_req.ready 221 // Bank conflict on data arrays 222 val s2_nack_data = RegEnable(!io.banked_data_read.ready, s1_fire) 223 val s2_nack = s2_nack_hit || s2_nack_no_mshr || s2_nack_data 224 225 val banked_data_resp = io.banked_data_resp 226 val s2_bank_addr = addr_to_dcache_bank(s2_paddr) 227 val banked_data_resp_word = Mux1H(s2_bank_oh, io.banked_data_resp) // io.banked_data_resp(s2_bank_addr) 228 dontTouch(s2_bank_addr) 229 230 val s2_instrtype = s2_req.instrtype 231 232 val s2_tag_error = dcacheParameters.tagCode.decode(s2_encTag).error // error reported by tag ecc check 233 val s2_flag_error = RegEnable(s1_flag_error, s1_fire) 234 235 val s2_hit = s2_tag_match && s2_has_permission && s2_hit_coh === s2_new_hit_coh 236 assert(!RegNext(s2_valid && (s2_tag_match && !s2_hit))) 237 assert(!RegNext(s2_valid && (s2_hit_dup_lsu =/= s2_hit))) 238 239 // only dump these signals when they are actually valid 240 dump_pipeline_valids("LoadPipe s2", "s2_hit", s2_valid && s2_hit) 241 dump_pipeline_valids("LoadPipe s2", "s2_nack", s2_valid && s2_nack) 242 dump_pipeline_valids("LoadPipe s2", "s2_nack_hit", s2_valid && s2_nack_hit) 243 dump_pipeline_valids("LoadPipe s2", "s2_nack_no_mshr", s2_valid && s2_nack_no_mshr) 244 245 val s2_can_send_miss_req = RegEnable(s1_will_send_miss_req, s1_fire) 246 247 // send load miss to miss queue 248 io.miss_req.valid := s2_valid && s2_can_send_miss_req 249 io.miss_req.bits := DontCare 250 io.miss_req.bits.source := s2_instrtype 251 io.miss_req.bits.cmd := s2_req.cmd 252 io.miss_req.bits.addr := get_block_addr(s2_paddr) 253 io.miss_req.bits.vaddr := s2_vaddr 254 io.miss_req.bits.way_en := s2_way_en 255 io.miss_req.bits.req_coh := s2_hit_coh 256 io.miss_req.bits.replace_coh := s2_repl_coh 257 io.miss_req.bits.replace_tag := s2_repl_tag 258 io.miss_req.bits.cancel := io.lsu.s2_kill || s2_tag_error 259 260 // send back response 261 val resp = Wire(ValidIO(new DCacheWordResp)) 262 resp.valid := s2_valid 263 resp.bits := DontCare 264 // resp.bits.data := s2_word_decoded 265 resp.bits.data := banked_data_resp_word.raw_data 266 // * on miss or nack, upper level should replay request 267 // but if we successfully sent the request to miss queue 268 // upper level does not need to replay request 269 // they can sit in load queue and wait for refill 270 // 271 // * report a miss if bank conflict is detected 272 val real_miss = !s2_hit_dup_lsu 273 resp.bits.miss := real_miss || io.bank_conflict_slow 274 // load pipe need replay when there is a bank conflict 275 resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack) || io.bank_conflict_slow 276 resp.bits.tag_error := s2_tag_error // report tag_error in load s2 277 278 XSPerfAccumulate("dcache_read_bank_conflict", io.bank_conflict_slow && s2_valid) 279 280 io.lsu.resp.valid := resp.valid 281 io.lsu.resp.bits := resp.bits 282 assert(RegNext(!(resp.valid && !io.lsu.resp.ready)), "lsu should be ready in s2") 283 284 when (resp.valid) { 285 resp.bits.dump() 286 } 287 288 io.lsu.debug_s1_hit_way := s1_tag_match_way 289 io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup 290 io.lsu.s1_bank_conflict := io.bank_conflict_fast 291 assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked") 292 293 // -------------------------------------------------------------------------------- 294 // stage 3 295 // -------------------------------------------------------------------------------- 296 // report ecc error 297 298 val s3_valid = RegNext(s2_valid) 299 val s3_paddr = RegEnable(s2_paddr, s2_fire) 300 val s3_hit = RegEnable(s2_hit, s2_fire) 301 302 val s3_data_error = io.read_error_delayed // banked_data_resp_word.error && !bank_conflict 303 val s3_tag_error = RegEnable(s2_tag_error, s2_fire) 304 val s3_flag_error = RegEnable(s2_flag_error, s2_fire) 305 val s3_error = s3_tag_error || s3_flag_error || s3_data_error 306 307 // error_delayed signal will be used to update uop.exception 1 cycle after load writeback 308 resp.bits.error_delayed := s3_error && (s3_hit || s3_tag_error) && s3_valid 309 310 // report tag / data / l2 error (with paddr) to bus error unit 311 io.error := 0.U.asTypeOf(new L1CacheErrorInfo()) 312 io.error.report_to_beu := (s3_tag_error || s3_data_error) && s3_valid 313 io.error.paddr := s3_paddr 314 io.error.source.tag := s3_tag_error 315 io.error.source.data := s3_data_error 316 io.error.source.l2 := s3_flag_error 317 io.error.opType.load := true.B 318 // report tag error / l2 corrupted to CACHE_ERROR csr 319 io.error.valid := s3_error && s3_valid 320 321 // update plru, report error in s3 322 323 io.replace_access.valid := RegNext(RegNext(RegNext(io.meta_read.fire()) && s1_valid && !io.lsu.s1_kill) && !s2_nack_no_mshr) 324 io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr))) 325 io.replace_access.bits.way := RegNext(RegNext(Mux(s1_tag_match, OHToUInt(s1_tag_match_way), io.replace_way.way))) 326 327 // -------------------------------------------------------------------------------- 328 // Debug logging functions 329 def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool, 330 req: DCacheWordReq ) = { 331 when (valid) { 332 XSDebug(s"$pipeline_stage_name: ") 333 req.dump() 334 } 335 } 336 337 def dump_pipeline_valids(pipeline_stage_name: String, signal_name: String, valid: Bool) = { 338 when (valid) { 339 XSDebug(s"$pipeline_stage_name $signal_name\n") 340 } 341 } 342 343 // performance counters 344 XSPerfAccumulate("load_req", io.lsu.req.fire()) 345 XSPerfAccumulate("load_s1_kill", s1_fire && io.lsu.s1_kill) 346 XSPerfAccumulate("load_hit_way", s1_fire && s1_tag_match) 347 XSPerfAccumulate("load_replay", io.lsu.resp.fire() && resp.bits.replay) 348 XSPerfAccumulate("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data) 349 XSPerfAccumulate("load_replay_for_no_mshr", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr) 350 XSPerfAccumulate("load_replay_for_conflict", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow) 351 XSPerfAccumulate("load_hit", io.lsu.resp.fire() && !real_miss) 352 XSPerfAccumulate("load_miss", io.lsu.resp.fire() && real_miss) 353 XSPerfAccumulate("load_succeed", io.lsu.resp.fire() && !resp.bits.miss && !resp.bits.replay) 354 XSPerfAccumulate("load_miss_or_conflict", io.lsu.resp.fire() && resp.bits.miss) 355 XSPerfAccumulate("actual_ld_fast_wakeup", s1_fire && s1_tag_match && !io.disable_ld_fast_wakeup) 356 XSPerfAccumulate("ideal_ld_fast_wakeup", io.banked_data_read.fire() && s1_tag_match) 357 358 val perfEvents = Seq( 359 ("load_req ", io.lsu.req.fire() ), 360 ("load_replay ", io.lsu.resp.fire() && resp.bits.replay ), 361 ("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data ), 362 ("load_replay_for_no_mshr ", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr ), 363 ("load_replay_for_conflict ", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow ), 364 ) 365 generatePerfEvent() 366} 367