1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientMetadata 23import utils.{HasPerfEvents, XSDebug, XSPerfAccumulate} 24import utility.ParallelPriorityMux 25import xiangshan.L1CacheErrorInfo 26import xiangshan.cache.dcache.{DCacheWPU, IdealWPU} 27 28class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPerfEvents { 29 val io = IO(new DCacheBundle { 30 // incoming requests 31 val lsu = Flipped(new DCacheLoadIO) 32 // req got nacked in stage 0? 33 val nack = Input(Bool()) 34 35 // meta and data array read port 36 val meta_read = DecoupledIO(new MetaReadReq) 37 val meta_resp = Input(Vec(nWays, new Meta)) 38 val extra_meta_resp = Input(Vec(nWays, new DCacheExtraMeta)) 39 40 val tag_read = DecoupledIO(new TagReadReq) 41 val tag_resp = Input(Vec(nWays, UInt(encTagBits.W))) 42 43 val banked_data_read = DecoupledIO(new L1BankedDataReadReq) 44 val banked_data_resp = Input(new L1BankedDataReadResult()) 45 val read_error_delayed = Input(Bool()) 46 47 // access bit update 48 val access_flag_write = DecoupledIO(new FlagMetaWriteReq) 49 50 // banked data read conflict 51 val bank_conflict_slow = Input(Bool()) 52 val bank_conflict_fast = Input(Bool()) 53 54 // send miss request to miss queue 55 val miss_req = DecoupledIO(new MissReq) 56 val miss_resp = Input(new MissResp) 57 58 // update state vec in replacement algo 59 val replace_access = ValidIO(new ReplacementAccessBundle) 60 // find the way to be replaced 61 val replace_way = new ReplacementWayReqIO 62 63 // load fast wakeup should be disabled when data read is not ready 64 val disable_ld_fast_wakeup = Input(Bool()) 65 66 // ecc error 67 val error = Output(new L1CacheErrorInfo()) 68 69 // // debug_ls_info 70 // val debug_s2_cache_miss = Bool() 71 }) 72 73 assert(RegNext(io.meta_read.ready)) 74 75 val s1_ready = Wire(Bool()) 76 val s2_ready = Wire(Bool()) 77 // LSU requests 78 // it you got nacked, you can directly passdown 79 val not_nacked_ready = io.meta_read.ready && io.tag_read.ready && s1_ready 80 val nacked_ready = true.B 81 82 // ready can wait for valid 83 io.lsu.req.ready := (!io.nack && not_nacked_ready) || (io.nack && nacked_ready) 84 io.meta_read.valid := io.lsu.req.fire() && !io.nack 85 io.tag_read.valid := io.lsu.req.fire() && !io.nack 86 87 val meta_read = io.meta_read.bits 88 val tag_read = io.tag_read.bits 89 90 // Tag read for new requests 91 meta_read.idx := get_idx(io.lsu.req.bits.addr) 92 meta_read.way_en := ~0.U(nWays.W) 93 // meta_read.tag := DontCare 94 95 tag_read.idx := get_idx(io.lsu.req.bits.addr) 96 tag_read.way_en := ~0.U(nWays.W) 97 98 // Pipeline 99 // -------------------------------------------------------------------------------- 100 // stage 0 101 // -------------------------------------------------------------------------------- 102 // read tag 103 104 val s0_valid = io.lsu.req.fire() 105 val s0_req = io.lsu.req.bits 106 val s0_fire = s0_valid && s1_ready 107 val s0_vaddr = s0_req.addr 108 val s0_replayCarry = s0_req.replayCarry 109 assert(RegNext(!(s0_valid && (s0_req.cmd =/= MemoryOpConstants.M_XRD && s0_req.cmd =/= MemoryOpConstants.M_PFR && s0_req.cmd =/= MemoryOpConstants.M_PFW))), "LoadPipe only accepts load req / softprefetch read or write!") 110 dump_pipeline_reqs("LoadPipe s0", s0_valid, s0_req) 111 112 // -------------------------------------------------------------------------------- 113 // stage 1 114 // -------------------------------------------------------------------------------- 115 // tag match, read data 116 117 val s1_valid = RegInit(false.B) 118 val s1_req = RegEnable(s0_req, s0_fire) 119 // in stage 1, load unit gets the physical address 120 val s1_paddr_dup_lsu = io.lsu.s1_paddr_dup_lsu 121 val s1_paddr_dup_dcache = io.lsu.s1_paddr_dup_dcache 122 // LSU may update the address from io.lsu.s1_paddr, which affects the bank read enable only. 123 val s1_vaddr = Cat(s1_req.addr(PAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) 124 val s1_bank_oh = UIntToOH(addr_to_dcache_bank(s1_vaddr)) 125 val s1_nack = RegNext(io.nack) 126 val s1_nack_data = !io.banked_data_read.ready 127 val s1_fire = s1_valid && s2_ready 128 s1_ready := !s1_valid || s1_fire 129 130 when (s0_fire) { s1_valid := true.B } 131 .elsewhen (s1_fire) { s1_valid := false.B } 132 133 dump_pipeline_reqs("LoadPipe s1", s1_valid, s1_req) 134 135 // tag check 136 val meta_resp = io.meta_resp 137 val tag_resp = io.tag_resp.map(r => r(tagBits - 1, 0)) 138 def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) 139 140 // dcache side tag match 141 /* // just ideal situation 142 val idealWPU = Module(new IdealWPU) 143 val s1_vaddr_dup_dc = Wire(UInt(PAddrBits.W)) 144 s1_vaddr_dup_dc := RegEnable(s0_req.addr, s0_fire) 145 idealWPU.io.req.bits.vaddr := s1_vaddr_dup_dc 146 idealWPU.io.req.valid := true.B 147 idealWPU.io.idealIf.s1_tag_resp := tag_resp 148 idealWPU.io.idealIf.s1_meta_resp := meta_resp 149 idealWPU.io.idealIf.s1_real_tag := get_tag(s1_paddr_dup_dcache) 150 */ 151 // real wpu 152 val wpu = Module(new DCacheWPU) 153 // req in s0 154 wpu.io.req.bits.vaddr := s0_vaddr 155 wpu.io.req.bits.replayCarry := s0_replayCarry 156 wpu.io.req.valid := s0_valid 157 // check in s1 158 wpu.io.check.bits.s1_tag_resp := tag_resp 159 wpu.io.check.bits.s1_meta_resp := meta_resp 160 wpu.io.check.bits.s1_real_tag := get_tag(s1_paddr_dup_dcache) 161 wpu.io.check.valid := s1_valid 162 // correct in s2 163 val s2_wpu_pred_fail = wpu.io.s2_pred_fail 164 val s2_real_way_en = wpu.io.s2_real_way_en 165 166 // resp in s1 167 val s1_tag_match_way_dup_dc = Wire(UInt(nWays.W)) 168 val s1_tag_match_way_dup_lsu = Wire(UInt(nWays.W)) 169 when (wpu.io.resp.valid){ 170 s1_tag_match_way_dup_dc := wpu.io.resp.bits.predict_way_en 171 s1_tag_match_way_dup_lsu := wpu.io.resp.bits.predict_way_en 172 }.otherwise { 173 val s1_tag_eq_way_dup_dc = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_dcache))).asUInt 174 s1_tag_match_way_dup_dc := wayMap((w: Int) => s1_tag_eq_way_dup_dc(w) && meta_resp(w).coh.isValid()).asUInt 175 176 // lsu side tag match 177 val s1_tag_eq_way_dup_lsu = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_lsu))).asUInt 178 s1_tag_match_way_dup_lsu := wayMap((w: Int) => s1_tag_eq_way_dup_lsu(w) && meta_resp(w).coh.isValid()).asUInt 179 } 180 val s1_tag_match_dup_dc = s1_tag_match_way_dup_dc.orR 181 val s1_tag_match_dup_lsu = s1_tag_match_way_dup_lsu.orR 182 assert(RegNext(!s1_valid || PopCount(s1_tag_match_way_dup_dc) <= 1.U), "tag should not match with more than 1 way") 183 184 val s1_fake_meta = Wire(new Meta) 185 // s1_fake_meta.tag := get_tag(s1_paddr_dup_dcache) 186 s1_fake_meta.coh := ClientMetadata.onReset 187 val s1_fake_tag = get_tag(s1_paddr_dup_dcache) 188 189 // when there are no tag match, we give it a Fake Meta 190 // this simplifies our logic in s2 stage 191 val s1_hit_meta = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => meta_resp(w))), s1_fake_meta) 192 val s1_hit_coh = s1_hit_meta.coh 193 val s1_hit_error = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).error)), false.B) 194 val s1_hit_prefetch = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).prefetch)), false.B) 195 val s1_hit_access = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).access)), false.B) 196 197 io.replace_way.set.valid := RegNext(s0_fire) 198 io.replace_way.set.bits := get_idx(s1_vaddr) 199 200 val s1_invalid_vec = wayMap(w => !meta_resp(w).coh.isValid()) 201 val s1_have_invalid_way = s1_invalid_vec.asUInt.orR 202 val s1_invalid_way_en = ParallelPriorityMux(s1_invalid_vec.zipWithIndex.map(x => x._1 -> UIntToOH(x._2.U(nWays.W)))) 203 val s1_repl_way_en_oh = Mux(s1_have_invalid_way, s1_invalid_way_en, UIntToOH(io.replace_way.way)) 204 val s1_repl_way_en_enc = OHToUInt(s1_repl_way_en_oh) 205 val s1_repl_tag = Mux1H(s1_repl_way_en_oh, wayMap(w => tag_resp(w))) 206 val s1_repl_coh = Mux1H(s1_repl_way_en_oh, wayMap(w => meta_resp(w).coh)) 207 val s1_repl_extra_meta = Mux1H(s1_repl_way_en_oh, wayMap(w => io.extra_meta_resp(w))) 208 209 val s1_need_replacement = !s1_tag_match_dup_dc 210 val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en_oh, s1_tag_match_way_dup_dc) 211 val s1_coh = Mux(s1_need_replacement, s1_repl_coh, s1_hit_coh) 212 val s1_tag = Mux(s1_need_replacement, s1_repl_tag, get_tag(s1_paddr_dup_dcache)) 213 214 XSPerfAccumulate("load_has_invalid_way_but_select_valid_way", io.replace_way.set.valid && wayMap(w => !meta_resp(w).coh.isValid()).asUInt.orR && s1_need_replacement && s1_repl_coh.isValid()) 215 XSPerfAccumulate("load_using_replacement", io.replace_way.set.valid && s1_need_replacement) 216 217 // data read 218 io.banked_data_read.valid := s1_fire && !s1_nack 219 io.banked_data_read.bits.addr := s1_vaddr 220 io.banked_data_read.bits.way_en := s1_tag_match_way_dup_dc 221 222 // get s1_will_send_miss_req in lpad_s1 223 val s1_has_permission = s1_hit_coh.onAccess(s1_req.cmd)._1 224 val s1_new_hit_coh = s1_hit_coh.onAccess(s1_req.cmd)._3 225 val s1_hit = s1_tag_match_dup_dc && s1_has_permission && s1_hit_coh === s1_new_hit_coh 226 val s1_will_send_miss_req = s1_valid && !s1_nack && !s1_nack_data && !s1_hit 227 228 // check ecc error 229 val s1_encTag = Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.tag_resp(w))) 230 val s1_flag_error = Mux(s1_need_replacement, false.B, s1_hit_error) // error reported by exist dcache error bit 231 232 // -------------------------------------------------------------------------------- 233 // stage 2 234 // -------------------------------------------------------------------------------- 235 // return data 236 237 // val s2_valid = RegEnable(next = s1_valid && !io.lsu.s1_kill, init = false.B, enable = s1_fire) 238 val s2_valid = RegInit(false.B) 239 val s2_req = RegEnable(s1_req, s1_fire) 240 val s2_paddr = RegEnable(s1_paddr_dup_dcache, s1_fire) 241 val s2_vaddr = RegEnable(s1_vaddr, s1_fire) 242 val s2_bank_oh = RegEnable(s1_bank_oh, s1_fire) 243 val s2_bank_oh_dup_0 = RegEnable(s1_bank_oh, s1_fire) 244 s2_ready := true.B 245 246 val s2_fire = s2_valid 247 248 when (s1_fire) { s2_valid := !io.lsu.s1_kill } 249 .elsewhen(io.lsu.resp.fire()) { s2_valid := false.B } 250 251 dump_pipeline_reqs("LoadPipe s2", s2_valid, s2_req) 252 253 254 // hit, miss, nack, permission checking 255 // dcache side tag match 256 val s2_tag_match_way = RegEnable(s1_tag_match_way_dup_dc, s1_fire) 257 val s2_tag_match = RegEnable(s1_tag_match_dup_dc, s1_fire) 258 259 // lsu side tag match 260 val s2_hit_dup_lsu = RegNext(s1_tag_match_dup_lsu) 261 262 io.lsu.s2_hit := s2_hit_dup_lsu && !s2_wpu_pred_fail 263 264 val s2_hit_meta = RegEnable(s1_hit_meta, s1_fire) 265 val s2_hit_coh = RegEnable(s1_hit_coh, s1_fire) 266 val s2_has_permission = s2_hit_coh.onAccess(s2_req.cmd)._1 // for write prefetch 267 val s2_new_hit_coh = s2_hit_coh.onAccess(s2_req.cmd)._3 // for write prefetch 268 269 val s2_way_en = RegEnable(s1_way_en, s1_fire) 270 val s2_repl_coh = RegEnable(s1_repl_coh, s1_fire) 271 val s2_repl_tag = RegEnable(s1_repl_tag, s1_fire) 272 val s2_repl_extra_meta = RegEnable(s1_repl_extra_meta, s1_fire) // not used for now 273 val s2_encTag = RegEnable(s1_encTag, s1_fire) 274 275 // when req got nacked, upper levels should replay this request 276 // nacked or not 277 val s2_nack_hit = RegEnable(s1_nack, s1_fire) 278 // can no allocate mshr for load miss 279 val s2_nack_no_mshr = io.miss_req.valid && !io.miss_req.ready 280 // Bank conflict on data arrays 281 val s2_nack_data = RegEnable(!io.banked_data_read.ready, s1_fire) 282 val s2_nack = s2_nack_hit || s2_nack_no_mshr || s2_nack_data 283 // s2 miss merged 284 val s2_miss_merged = io.miss_req.valid && io.miss_resp.merged 285 286 val s2_bank_addr = addr_to_dcache_bank(s2_paddr) 287 dontTouch(s2_bank_addr) 288 289 val s2_instrtype = s2_req.instrtype 290 291 val s2_tag_error = dcacheParameters.tagCode.decode(s2_encTag).error // error reported by tag ecc check 292 val s2_flag_error = RegEnable(s1_flag_error, s1_fire) 293 294 val s2_hit_prefetch = RegEnable(s1_hit_prefetch, s1_fire) 295 val s2_hit_access = RegEnable(s1_hit_access, s1_fire) 296 297 val s2_hit = s2_tag_match && s2_has_permission && s2_hit_coh === s2_new_hit_coh && !s2_wpu_pred_fail 298 299 // only dump these signals when they are actually valid 300 dump_pipeline_valids("LoadPipe s2", "s2_hit", s2_valid && s2_hit) 301 dump_pipeline_valids("LoadPipe s2", "s2_nack", s2_valid && s2_nack) 302 dump_pipeline_valids("LoadPipe s2", "s2_nack_hit", s2_valid && s2_nack_hit) 303 dump_pipeline_valids("LoadPipe s2", "s2_nack_no_mshr", s2_valid && s2_nack_no_mshr) 304 305 val s2_can_send_miss_req = RegEnable(s1_will_send_miss_req, s1_fire) 306 307 // send load miss to miss queue 308 io.miss_req.valid := s2_valid && s2_can_send_miss_req && !s2_wpu_pred_fail 309 io.miss_req.bits := DontCare 310 io.miss_req.bits.source := s2_instrtype 311 io.miss_req.bits.cmd := s2_req.cmd 312 io.miss_req.bits.addr := get_block_addr(s2_paddr) 313 io.miss_req.bits.vaddr := s2_vaddr 314 io.miss_req.bits.way_en := s2_way_en 315 io.miss_req.bits.req_coh := s2_hit_coh 316 io.miss_req.bits.replace_coh := s2_repl_coh 317 io.miss_req.bits.replace_tag := s2_repl_tag 318 io.miss_req.bits.cancel := io.lsu.s2_kill || s2_tag_error 319 io.miss_req.bits.pc := io.lsu.s2_pc 320 321 // send back response 322 val resp = Wire(ValidIO(new DCacheWordResp)) 323 resp.valid := s2_valid 324 resp.bits := DontCare 325 // resp.bits.data := s2_word_decoded 326 // resp.bits.data := banked_data_resp_word.raw_data 327 // * on miss or nack, upper level should replay request 328 // but if we successfully sent the request to miss queue 329 // upper level does not need to replay request 330 // they can sit in load queue and wait for refill 331 // 332 // * report a miss if bank conflict is detected 333 val real_miss = Wire(Bool()) 334 when (wpu.io.resp.valid){ 335 real_miss := !s2_real_way_en.orR 336 }.otherwise{ 337 real_miss := !s2_hit_dup_lsu 338 } 339 // io.debug_s2_cache_miss := real_miss 340 resp.bits.miss := real_miss || io.bank_conflict_slow || s2_wpu_pred_fail 341 io.lsu.s2_first_hit := s2_req.isFirstIssue && s2_hit 342 // load pipe need replay when there is a bank conflict or wpu predict fail 343 resp.bits.replay := (resp.bits.miss && (!io.miss_req.fire() || s2_nack)) || io.bank_conflict_slow || s2_wpu_pred_fail 344 resp.bits.replayCarry.valid := resp.bits.miss 345 resp.bits.replayCarry.real_way_en := s2_real_way_en 346 resp.bits.meta_prefetch := s2_hit_prefetch 347 resp.bits.meta_access := s2_hit_access 348 resp.bits.tag_error := s2_tag_error // report tag_error in load s2 349 resp.bits.mshr_id := io.miss_resp.id 350 resp.bits.debug_robIdx := s2_req.debug_robIdx 351 352 XSPerfAccumulate("wpu_pred_fail", s2_wpu_pred_fail && s2_valid) 353 XSPerfAccumulate("dcache_read_bank_conflict", io.bank_conflict_slow && s2_valid) 354 XSPerfAccumulate("dcache_read_from_prefetched_line", s2_valid && s2_hit_prefetch && !resp.bits.miss) 355 XSPerfAccumulate("dcache_first_read_from_prefetched_line", s2_valid && s2_hit_prefetch && !resp.bits.miss && !s2_hit_access) 356 357 io.lsu.resp.valid := resp.valid 358 io.lsu.resp.bits := resp.bits 359 assert(RegNext(!(resp.valid && !io.lsu.resp.ready)), "lsu should be ready in s2") 360 361 when (resp.valid) { 362 resp.bits.dump() 363 } 364 365 io.lsu.debug_s1_hit_way := s1_tag_match_way_dup_dc 366 io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup 367 io.lsu.s2_bank_conflict := io.bank_conflict_slow 368 assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked") 369 370 // -------------------------------------------------------------------------------- 371 // stage 3 372 // -------------------------------------------------------------------------------- 373 // report ecc error and get selected dcache data 374 375 val s3_valid = RegNext(s2_valid) 376 val s3_vaddr = RegEnable(s2_vaddr, s2_fire) 377 val s3_paddr = RegEnable(s2_paddr, s2_fire) 378 val s3_hit = RegEnable(s2_hit, s2_fire) 379 val s3_tag_match_way = RegEnable(s2_tag_match_way, s2_fire) 380 381 val s3_banked_data_resp_word = io.banked_data_resp.raw_data 382 val s3_data_error = io.read_error_delayed && s3_hit // banked_data_resp_word.error && !bank_conflict 383 val s3_tag_error = RegEnable(s2_tag_error, s2_fire) 384 val s3_flag_error = RegEnable(s2_flag_error, s2_fire) 385 val s3_error = s3_tag_error || s3_flag_error || s3_data_error 386 387 // error_delayed signal will be used to update uop.exception 1 cycle after load writeback 388 resp.bits.error_delayed := s3_error && (s3_hit || s3_tag_error) && s3_valid 389 resp.bits.data_delayed := s3_banked_data_resp_word 390 391 // report tag / data / l2 error (with paddr) to bus error unit 392 io.error := 0.U.asTypeOf(new L1CacheErrorInfo()) 393 io.error.report_to_beu := (s3_tag_error || s3_data_error) && s3_valid 394 io.error.paddr := s3_paddr 395 io.error.source.tag := s3_tag_error 396 io.error.source.data := s3_data_error 397 io.error.source.l2 := s3_flag_error 398 io.error.opType.load := true.B 399 // report tag error / l2 corrupted to CACHE_ERROR csr 400 io.error.valid := s3_error && s3_valid 401 402 // update plru in s3 403 if (!cfg.updateReplaceOn2ndmiss) { 404 // replacement is only updated on 1st miss 405 io.replace_access.valid := RegNext(RegNext( 406 RegNext(io.meta_read.fire()) && s1_valid && !io.lsu.s1_kill) && 407 !s2_nack_no_mshr && 408 !s2_miss_merged 409 ) 410 io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr))) 411 io.replace_access.bits.way := RegNext(RegNext(Mux(s1_tag_match_dup_dc, OHToUInt(s1_tag_match_way_dup_dc), s1_repl_way_en_enc))) 412 } else { 413 // replacement is updated on both 1st and 2nd miss 414 // timing is worse than !cfg.updateReplaceOn2ndmiss 415 io.replace_access.valid := RegNext(RegNext( 416 RegNext(io.meta_read.fire()) && s1_valid && !io.lsu.s1_kill) && 417 !s2_nack_no_mshr && 418 // replacement is updated on 2nd miss only when this req is firstly issued 419 (!s2_miss_merged || s2_req.isFirstIssue) 420 ) 421 io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr))) 422 io.replace_access.bits.way := RegNext( 423 Mux( 424 RegNext(s1_tag_match_dup_dc), 425 RegNext(OHToUInt(s1_tag_match_way_dup_dc)), // if hit, access hit way in plru 426 Mux( // if miss 427 !s2_miss_merged, 428 RegNext(s1_repl_way_en_enc), // 1st fire: access new selected replace way 429 OHToUInt(io.miss_resp.repl_way_en) // 2nd fire: access replace way selected at miss queue allocate time 430 ) 431 ) 432 ) 433 } 434 435 // update access bit 436 io.access_flag_write.valid := s3_valid && s3_hit 437 io.access_flag_write.bits.idx := get_idx(s3_vaddr) 438 io.access_flag_write.bits.way_en := s3_tag_match_way 439 io.access_flag_write.bits.flag := true.B 440 441 // -------------------------------------------------------------------------------- 442 // Debug logging functions 443 def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool, 444 req: DCacheWordReq ) = { 445 when (valid) { 446 XSDebug(s"$pipeline_stage_name: ") 447 req.dump() 448 } 449 } 450 451 def dump_pipeline_valids(pipeline_stage_name: String, signal_name: String, valid: Bool) = { 452 when (valid) { 453 XSDebug(s"$pipeline_stage_name $signal_name\n") 454 } 455 } 456 457 // performance counters 458 XSPerfAccumulate("load_req", io.lsu.req.fire()) 459 XSPerfAccumulate("load_s1_kill", s1_fire && io.lsu.s1_kill) 460 XSPerfAccumulate("load_hit_way", s1_fire && s1_tag_match_dup_dc) 461 XSPerfAccumulate("load_replay", io.lsu.resp.fire() && resp.bits.replay) 462 XSPerfAccumulate("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data) 463 XSPerfAccumulate("load_replay_for_no_mshr", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr) 464 XSPerfAccumulate("load_replay_for_conflict", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow) 465 XSPerfAccumulate("load_hit", io.lsu.resp.fire() && !real_miss) 466 XSPerfAccumulate("load_miss", io.lsu.resp.fire() && real_miss) 467 XSPerfAccumulate("load_succeed", io.lsu.resp.fire() && !resp.bits.miss && !resp.bits.replay) 468 XSPerfAccumulate("load_miss_or_conflict", io.lsu.resp.fire() && resp.bits.miss) 469 XSPerfAccumulate("actual_ld_fast_wakeup", s1_fire && s1_tag_match_dup_dc && !io.disable_ld_fast_wakeup) 470 XSPerfAccumulate("ideal_ld_fast_wakeup", io.banked_data_read.fire() && s1_tag_match_dup_dc) 471 472 val perfEvents = Seq( 473 ("load_req ", io.lsu.req.fire() ), 474 ("load_replay ", io.lsu.resp.fire() && resp.bits.replay ), 475 ("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data ), 476 ("load_replay_for_no_mshr ", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr ), 477 ("load_replay_for_conflict ", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow ), 478 ) 479 generatePerfEvent() 480} 481