1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientMetadata 23import utils.{HasPerfEvents, XSDebug, XSPerfAccumulate} 24import xiangshan.L1CacheErrorInfo 25import xiangshan.cache.dcache.{DCacheWPU, IdealWPU} 26 27class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPerfEvents { 28 val io = IO(new DCacheBundle { 29 // incoming requests 30 val lsu = Flipped(new DCacheLoadIO) 31 // req got nacked in stage 0? 32 val nack = Input(Bool()) 33 34 // meta and data array read port 35 val meta_read = DecoupledIO(new MetaReadReq) 36 val meta_resp = Input(Vec(nWays, new Meta)) 37 val error_flag_resp = Input(Vec(nWays, Bool())) 38 39 val tag_read = DecoupledIO(new TagReadReq) 40 val tag_resp = Input(Vec(nWays, UInt(encTagBits.W))) 41 42 val banked_data_read = DecoupledIO(new L1BankedDataReadReq) 43 val banked_data_resp = Input(new L1BankedDataReadResult()) 44 val read_error_delayed = Input(Bool()) 45 46 // banked data read conflict 47 val bank_conflict_slow = Input(Bool()) 48 val bank_conflict_fast = Input(Bool()) 49 50 // send miss request to miss queue 51 val miss_req = DecoupledIO(new MissReq) 52 val miss_resp = Input(new MissResp) 53 54 // update state vec in replacement algo 55 val replace_access = ValidIO(new ReplacementAccessBundle) 56 // find the way to be replaced 57 val replace_way = new ReplacementWayReqIO 58 59 // load fast wakeup should be disabled when data read is not ready 60 val disable_ld_fast_wakeup = Input(Bool()) 61 62 // ecc error 63 val error = Output(new L1CacheErrorInfo()) 64 }) 65 66 assert(RegNext(io.meta_read.ready)) 67 68 val s1_ready = Wire(Bool()) 69 val s2_ready = Wire(Bool()) 70 // LSU requests 71 // it you got nacked, you can directly passdown 72 val not_nacked_ready = io.meta_read.ready && io.tag_read.ready && s1_ready 73 val nacked_ready = true.B 74 75 // ready can wait for valid 76 io.lsu.req.ready := (!io.nack && not_nacked_ready) || (io.nack && nacked_ready) 77 io.meta_read.valid := io.lsu.req.fire() && !io.nack 78 io.tag_read.valid := io.lsu.req.fire() && !io.nack 79 80 val meta_read = io.meta_read.bits 81 val tag_read = io.tag_read.bits 82 83 // Tag read for new requests 84 meta_read.idx := get_idx(io.lsu.req.bits.addr) 85 meta_read.way_en := ~0.U(nWays.W) 86 // meta_read.tag := DontCare 87 88 tag_read.idx := get_idx(io.lsu.req.bits.addr) 89 tag_read.way_en := ~0.U(nWays.W) 90 91 // Pipeline 92 // -------------------------------------------------------------------------------- 93 // stage 0 94 // -------------------------------------------------------------------------------- 95 // read tag 96 97 val s0_valid = io.lsu.req.fire() 98 val s0_req = io.lsu.req.bits 99 val s0_fire = s0_valid && s1_ready 100 val s0_vaddr = s0_req.addr 101 val s0_replayCarry = s0_req.replayCarry 102 assert(RegNext(!(s0_valid && (s0_req.cmd =/= MemoryOpConstants.M_XRD && s0_req.cmd =/= MemoryOpConstants.M_PFR && s0_req.cmd =/= MemoryOpConstants.M_PFW))), "LoadPipe only accepts load req / softprefetch read or write!") 103 dump_pipeline_reqs("LoadPipe s0", s0_valid, s0_req) 104 105 // -------------------------------------------------------------------------------- 106 // stage 1 107 // -------------------------------------------------------------------------------- 108 // tag match, read data 109 110 val s1_valid = RegInit(false.B) 111 val s1_req = RegEnable(s0_req, s0_fire) 112 // in stage 1, load unit gets the physical address 113 val s1_paddr_dup_lsu = io.lsu.s1_paddr_dup_lsu 114 val s1_paddr_dup_dcache = io.lsu.s1_paddr_dup_dcache 115 // LSU may update the address from io.lsu.s1_paddr, which affects the bank read enable only. 116 val s1_vaddr = Cat(s1_req.addr(PAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) 117 val s1_bank_oh = UIntToOH(addr_to_dcache_bank(s1_vaddr)) 118 val s1_nack = RegNext(io.nack) 119 val s1_nack_data = !io.banked_data_read.ready 120 val s1_fire = s1_valid && s2_ready 121 s1_ready := !s1_valid || s1_fire 122 123 when (s0_fire) { s1_valid := true.B } 124 .elsewhen (s1_fire) { s1_valid := false.B } 125 126 dump_pipeline_reqs("LoadPipe s1", s1_valid, s1_req) 127 128 // tag check 129 val meta_resp = io.meta_resp 130 val tag_resp = io.tag_resp.map(r => r(tagBits - 1, 0)) 131 def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) 132 133 // dcache side tag match 134 /* // just ideal situation 135 val idealWPU = Module(new IdealWPU) 136 val s1_vaddr_dup_dc = Wire(UInt(PAddrBits.W)) 137 s1_vaddr_dup_dc := RegEnable(s0_req.addr, s0_fire) 138 idealWPU.io.req.bits.vaddr := s1_vaddr_dup_dc 139 idealWPU.io.req.valid := true.B 140 idealWPU.io.idealIf.s1_tag_resp := tag_resp 141 idealWPU.io.idealIf.s1_meta_resp := meta_resp 142 idealWPU.io.idealIf.s1_real_tag := get_tag(s1_paddr_dup_dcache) 143 */ 144 // real wpu 145 val wpu = Module(new DCacheWPU) 146 // req in s0 147 wpu.io.req.bits.vaddr := s0_vaddr 148 wpu.io.req.bits.replayCarry := s0_replayCarry 149 wpu.io.req.valid := s0_valid 150 // check in s1 151 wpu.io.check.bits.s1_tag_resp := tag_resp 152 wpu.io.check.bits.s1_meta_resp := meta_resp 153 wpu.io.check.bits.s1_real_tag := get_tag(s1_paddr_dup_dcache) 154 wpu.io.check.valid := s1_valid 155 // correct in s2 156 val s2_wpu_pred_fail = wpu.io.s2_pred_fail 157 val s2_real_way_en = wpu.io.s2_real_way_en 158 159 // resp in s1 160 val s1_tag_match_way_dup_dc = Wire(UInt(nWays.W)) 161 val s1_tag_match_way_dup_lsu = Wire(UInt(nWays.W)) 162 when (wpu.io.resp.valid){ 163 s1_tag_match_way_dup_dc := wpu.io.resp.bits.predict_way_en 164 s1_tag_match_way_dup_lsu := wpu.io.resp.bits.predict_way_en 165 }.otherwise { 166 val s1_tag_eq_way_dup_dc = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_dcache))).asUInt 167 s1_tag_match_way_dup_dc := wayMap((w: Int) => s1_tag_eq_way_dup_dc(w) && meta_resp(w).coh.isValid()).asUInt 168 169 // lsu side tag match 170 val s1_tag_eq_way_dup_lsu = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_lsu))).asUInt 171 s1_tag_match_way_dup_lsu := wayMap((w: Int) => s1_tag_eq_way_dup_lsu(w) && meta_resp(w).coh.isValid()).asUInt 172 } 173 val s1_tag_match_dup_dc = s1_tag_match_way_dup_dc.orR 174 val s1_tag_match_dup_lsu = s1_tag_match_way_dup_lsu.orR 175 assert(RegNext(!s1_valid || PopCount(s1_tag_match_way_dup_dc) <= 1.U), "tag should not match with more than 1 way") 176 177 val s1_fake_meta = Wire(new Meta) 178// s1_fake_meta.tag := get_tag(s1_paddr_dup_dcache) 179 s1_fake_meta.coh := ClientMetadata.onReset 180 val s1_fake_tag = get_tag(s1_paddr_dup_dcache) 181 182 // when there are no tag match, we give it a Fake Meta 183 // this simplifies our logic in s2 stage 184 val s1_hit_meta = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => meta_resp(w))), s1_fake_meta) 185 val s1_hit_coh = s1_hit_meta.coh 186 val s1_hit_error = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.error_flag_resp(w))), false.B) 187 188 io.replace_way.set.valid := RegNext(s0_fire) 189 io.replace_way.set.bits := get_idx(s1_vaddr) 190 val s1_repl_way_en = UIntToOH(io.replace_way.way) 191 val s1_repl_tag = Mux1H(s1_repl_way_en, wayMap(w => tag_resp(w))) 192 val s1_repl_coh = Mux1H(s1_repl_way_en, wayMap(w => meta_resp(w).coh)) 193 194 val s1_need_replacement = !s1_tag_match_dup_dc 195 val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way_dup_dc) 196 val s1_coh = Mux(s1_need_replacement, s1_repl_coh, s1_hit_coh) 197 val s1_tag = Mux(s1_need_replacement, s1_repl_tag, get_tag(s1_paddr_dup_dcache)) 198 199 // data read 200 io.banked_data_read.valid := s1_fire && !s1_nack 201 io.banked_data_read.bits.addr := s1_vaddr 202 io.banked_data_read.bits.way_en := s1_tag_match_way_dup_dc 203 204 // get s1_will_send_miss_req in lpad_s1 205 val s1_has_permission = s1_hit_coh.onAccess(s1_req.cmd)._1 206 val s1_new_hit_coh = s1_hit_coh.onAccess(s1_req.cmd)._3 207 val s1_hit = s1_tag_match_dup_dc && s1_has_permission && s1_hit_coh === s1_new_hit_coh 208 val s1_will_send_miss_req = s1_valid && !s1_nack && !s1_nack_data && !s1_hit 209 210 // check ecc error 211 val s1_encTag = Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.tag_resp(w))) 212 val s1_flag_error = Mux(s1_need_replacement, false.B, s1_hit_error) // error reported by exist dcache error bit 213 214 // -------------------------------------------------------------------------------- 215 // stage 2 216 // -------------------------------------------------------------------------------- 217 // return data 218 219 // val s2_valid = RegEnable(next = s1_valid && !io.lsu.s1_kill, init = false.B, enable = s1_fire) 220 val s2_valid = RegInit(false.B) 221 val s2_req = RegEnable(s1_req, s1_fire) 222 val s2_paddr = RegEnable(s1_paddr_dup_dcache, s1_fire) 223 val s2_vaddr = RegEnable(s1_vaddr, s1_fire) 224 val s2_bank_oh = RegEnable(s1_bank_oh, s1_fire) 225 val s2_bank_oh_dup_0 = RegEnable(s1_bank_oh, s1_fire) 226 s2_ready := true.B 227 228 val s2_fire = s2_valid 229 230 when (s1_fire) { s2_valid := !io.lsu.s1_kill } 231 .elsewhen(io.lsu.resp.fire()) { s2_valid := false.B } 232 233 dump_pipeline_reqs("LoadPipe s2", s2_valid, s2_req) 234 235 // hit, miss, nack, permission checking 236 // dcache side tag match 237 val s2_tag_match_way = RegEnable(s1_tag_match_way_dup_dc, s1_fire) 238 val s2_tag_match = RegEnable(s1_tag_match_dup_dc, s1_fire) 239 240 // lsu side tag match 241 val s2_hit_dup_lsu = RegNext(s1_tag_match_dup_lsu) 242 243 io.lsu.s2_hit := s2_hit_dup_lsu && !s2_wpu_pred_fail 244 245 val s2_hit_meta = RegEnable(s1_hit_meta, s1_fire) 246 val s2_hit_coh = RegEnable(s1_hit_coh, s1_fire) 247 val s2_has_permission = s2_hit_coh.onAccess(s2_req.cmd)._1 // redundant 248 val s2_new_hit_coh = s2_hit_coh.onAccess(s2_req.cmd)._3 // redundant 249 250 val s2_way_en = RegEnable(s1_way_en, s1_fire) 251 val s2_repl_coh = RegEnable(s1_repl_coh, s1_fire) 252 val s2_repl_tag = RegEnable(s1_repl_tag, s1_fire) 253 val s2_encTag = RegEnable(s1_encTag, s1_fire) 254 255 // when req got nacked, upper levels should replay this request 256 // nacked or not 257 val s2_nack_hit = RegEnable(s1_nack, s1_fire) 258 // can no allocate mshr for load miss 259 val s2_nack_no_mshr = io.miss_req.valid && !io.miss_req.ready 260 // Bank conflict on data arrays 261 val s2_nack_data = RegEnable(!io.banked_data_read.ready, s1_fire) 262 val s2_nack = s2_nack_hit || s2_nack_no_mshr || s2_nack_data 263 264 val s2_bank_addr = addr_to_dcache_bank(s2_paddr) 265 dontTouch(s2_bank_addr) 266 267 val s2_instrtype = s2_req.instrtype 268 269 val s2_tag_error = dcacheParameters.tagCode.decode(s2_encTag).error // error reported by tag ecc check 270 val s2_flag_error = RegEnable(s1_flag_error, s1_fire) 271 272 val s2_hit = s2_tag_match && s2_has_permission && s2_hit_coh === s2_new_hit_coh && !s2_wpu_pred_fail 273 // assert(!RegNext(s2_valid && (s2_tag_match && !s2_hit))) 274 // assert(!RegNext(s2_valid && (s2_hit_dup_lsu =/= s2_hit))) 275 276 // only dump these signals when they are actually valid 277 dump_pipeline_valids("LoadPipe s2", "s2_hit", s2_valid && s2_hit) 278 dump_pipeline_valids("LoadPipe s2", "s2_nack", s2_valid && s2_nack) 279 dump_pipeline_valids("LoadPipe s2", "s2_nack_hit", s2_valid && s2_nack_hit) 280 dump_pipeline_valids("LoadPipe s2", "s2_nack_no_mshr", s2_valid && s2_nack_no_mshr) 281 282 val s2_can_send_miss_req = RegEnable(s1_will_send_miss_req, s1_fire) 283 284 // send load miss to miss queue 285 io.miss_req.valid := s2_valid && s2_can_send_miss_req && !s2_wpu_pred_fail 286 io.miss_req.bits := DontCare 287 io.miss_req.bits.source := s2_instrtype 288 io.miss_req.bits.cmd := s2_req.cmd 289 io.miss_req.bits.addr := get_block_addr(s2_paddr) 290 io.miss_req.bits.vaddr := s2_vaddr 291 io.miss_req.bits.way_en := s2_way_en 292 io.miss_req.bits.req_coh := s2_hit_coh 293 io.miss_req.bits.replace_coh := s2_repl_coh 294 io.miss_req.bits.replace_tag := s2_repl_tag 295 io.miss_req.bits.cancel := io.lsu.s2_kill || s2_tag_error 296 297 // send back response 298 val resp = Wire(ValidIO(new DCacheWordResp)) 299 resp.valid := s2_valid 300 resp.bits := DontCare 301 // resp.bits.data := s2_word_decoded 302 // resp.bits.data := banked_data_resp_word.raw_data 303 // * on miss or nack, upper level should replay request 304 // but if we successfully sent the request to miss queue 305 // upper level does not need to replay request 306 // they can sit in load queue and wait for refill 307 // 308 // * report a miss if bank conflict is detected 309 val real_miss = !s2_hit_dup_lsu 310 resp.bits.miss := real_miss || io.bank_conflict_slow || s2_wpu_pred_fail 311 // load pipe need replay when there is a bank conflict or wpu predict fail 312 resp.bits.replay := (resp.bits.miss && (!io.miss_req.fire() || s2_nack)) || io.bank_conflict_slow || s2_wpu_pred_fail 313 resp.bits.replayCarry.valid := resp.bits.miss 314 resp.bits.replayCarry.real_way_en := s2_real_way_en 315 resp.bits.tag_error := s2_tag_error // report tag_error in load s2 316 resp.bits.mshr_id := io.miss_resp.id 317 318 XSPerfAccumulate("dcache_read_bank_conflict", io.bank_conflict_slow && s2_valid) 319 XSPerfAccumulate("wpu_pred_fail", s2_wpu_pred_fail && s2_valid) 320 321 io.lsu.resp.valid := resp.valid 322 io.lsu.resp.bits := resp.bits 323 assert(RegNext(!(resp.valid && !io.lsu.resp.ready)), "lsu should be ready in s2") 324 325 when (resp.valid) { 326 resp.bits.dump() 327 } 328 329 io.lsu.debug_s1_hit_way := s1_tag_match_way_dup_dc 330 io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup 331 io.lsu.s1_bank_conflict := io.bank_conflict_fast 332 assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked") 333 334 // -------------------------------------------------------------------------------- 335 // stage 3 336 // -------------------------------------------------------------------------------- 337 // report ecc error and get selected dcache data 338 339 val s3_valid = RegNext(s2_valid) 340 val s3_paddr = RegEnable(s2_paddr, s2_fire) 341 val s3_hit = RegEnable(s2_hit, s2_fire) 342 343 val s3_banked_data_resp_word = io.banked_data_resp.raw_data 344 val s3_data_error = io.read_error_delayed // banked_data_resp_word.error && !bank_conflict 345 val s3_tag_error = RegEnable(s2_tag_error, s2_fire) 346 val s3_flag_error = RegEnable(s2_flag_error, s2_fire) 347 val s3_error = s3_tag_error || s3_flag_error || s3_data_error 348 349 // error_delayed signal will be used to update uop.exception 1 cycle after load writeback 350 resp.bits.error_delayed := s3_error && (s3_hit || s3_tag_error) && s3_valid 351 resp.bits.data_delayed := s3_banked_data_resp_word 352 353 // report tag / data / l2 error (with paddr) to bus error unit 354 io.error := 0.U.asTypeOf(new L1CacheErrorInfo()) 355 io.error.report_to_beu := (s3_tag_error || s3_data_error) && s3_valid 356 io.error.paddr := s3_paddr 357 io.error.source.tag := s3_tag_error 358 io.error.source.data := s3_data_error 359 io.error.source.l2 := s3_flag_error 360 io.error.opType.load := true.B 361 // report tag error / l2 corrupted to CACHE_ERROR csr 362 io.error.valid := s3_error && s3_valid 363 364 // update plru, report error in s3 365 366 io.replace_access.valid := RegNext(RegNext(RegNext(io.meta_read.fire()) && s1_valid && !io.lsu.s1_kill) && !s2_nack_no_mshr) 367 io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr))) 368 io.replace_access.bits.way := RegNext(RegNext(Mux(s1_tag_match_dup_dc, OHToUInt(s1_tag_match_way_dup_dc), io.replace_way.way))) 369 370 // -------------------------------------------------------------------------------- 371 // Debug logging functions 372 def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool, 373 req: DCacheWordReq ) = { 374 when (valid) { 375 XSDebug(s"$pipeline_stage_name: ") 376 req.dump() 377 } 378 } 379 380 def dump_pipeline_valids(pipeline_stage_name: String, signal_name: String, valid: Bool) = { 381 when (valid) { 382 XSDebug(s"$pipeline_stage_name $signal_name\n") 383 } 384 } 385 386 // performance counters 387 XSPerfAccumulate("load_req", io.lsu.req.fire()) 388 XSPerfAccumulate("load_s1_kill", s1_fire && io.lsu.s1_kill) 389 XSPerfAccumulate("load_hit_way", s1_fire && s1_tag_match_dup_dc) 390 XSPerfAccumulate("load_replay", io.lsu.resp.fire() && resp.bits.replay) 391 XSPerfAccumulate("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data) 392 XSPerfAccumulate("load_replay_for_no_mshr", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr) 393 XSPerfAccumulate("load_replay_for_conflict", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow) 394 XSPerfAccumulate("load_hit", io.lsu.resp.fire() && !real_miss) 395 XSPerfAccumulate("load_miss", io.lsu.resp.fire() && real_miss) 396 XSPerfAccumulate("load_succeed", io.lsu.resp.fire() && !resp.bits.miss && !resp.bits.replay) 397 XSPerfAccumulate("load_miss_or_conflict", io.lsu.resp.fire() && resp.bits.miss) 398 XSPerfAccumulate("actual_ld_fast_wakeup", s1_fire && s1_tag_match_dup_dc && !io.disable_ld_fast_wakeup) 399 XSPerfAccumulate("ideal_ld_fast_wakeup", io.banked_data_read.fire() && s1_tag_match_dup_dc) 400 401 val perfEvents = Seq( 402 ("load_req ", io.lsu.req.fire() ), 403 ("load_replay ", io.lsu.resp.fire() && resp.bits.replay ), 404 ("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data ), 405 ("load_replay_for_no_mshr ", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr ), 406 ("load_replay_for_conflict ", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow ), 407 ) 408 generatePerfEvent() 409} 410