1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientMetadata 23import utils.{HasPerfEvents, XSDebug, XSPerfAccumulate} 24import xiangshan.L1CacheErrorInfo 25import xiangshan.cache.dcache.{DCacheWPU, IdealWPU} 26 27class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPerfEvents { 28 val io = IO(new DCacheBundle { 29 // incoming requests 30 val lsu = Flipped(new DCacheLoadIO) 31 // req got nacked in stage 0? 32 val nack = Input(Bool()) 33 34 // meta and data array read port 35 val meta_read = DecoupledIO(new MetaReadReq) 36 val meta_resp = Input(Vec(nWays, new Meta)) 37 val extra_meta_resp = Input(Vec(nWays, new DCacheExtraMeta)) 38 39 val tag_read = DecoupledIO(new TagReadReq) 40 val tag_resp = Input(Vec(nWays, UInt(encTagBits.W))) 41 42 val banked_data_read = DecoupledIO(new L1BankedDataReadReq) 43 val banked_data_resp = Input(new L1BankedDataReadResult()) 44 val read_error_delayed = Input(Bool()) 45 46 // access bit update 47 val access_flag_write = DecoupledIO(new FlagMetaWriteReq) 48 49 // banked data read conflict 50 val bank_conflict_slow = Input(Bool()) 51 val bank_conflict_fast = Input(Bool()) 52 53 // send miss request to miss queue 54 val miss_req = DecoupledIO(new MissReq) 55 val miss_resp = Input(new MissResp) 56 57 // update state vec in replacement algo 58 val replace_access = ValidIO(new ReplacementAccessBundle) 59 // find the way to be replaced 60 val replace_way = new ReplacementWayReqIO 61 62 // load fast wakeup should be disabled when data read is not ready 63 val disable_ld_fast_wakeup = Input(Bool()) 64 65 // ecc error 66 val error = Output(new L1CacheErrorInfo()) 67 }) 68 69 assert(RegNext(io.meta_read.ready)) 70 71 val s1_ready = Wire(Bool()) 72 val s2_ready = Wire(Bool()) 73 // LSU requests 74 // it you got nacked, you can directly passdown 75 val not_nacked_ready = io.meta_read.ready && io.tag_read.ready && s1_ready 76 val nacked_ready = true.B 77 78 // ready can wait for valid 79 io.lsu.req.ready := (!io.nack && not_nacked_ready) || (io.nack && nacked_ready) 80 io.meta_read.valid := io.lsu.req.fire() && !io.nack 81 io.tag_read.valid := io.lsu.req.fire() && !io.nack 82 83 val meta_read = io.meta_read.bits 84 val tag_read = io.tag_read.bits 85 86 // Tag read for new requests 87 meta_read.idx := get_idx(io.lsu.req.bits.addr) 88 meta_read.way_en := ~0.U(nWays.W) 89 // meta_read.tag := DontCare 90 91 tag_read.idx := get_idx(io.lsu.req.bits.addr) 92 tag_read.way_en := ~0.U(nWays.W) 93 94 // Pipeline 95 // -------------------------------------------------------------------------------- 96 // stage 0 97 // -------------------------------------------------------------------------------- 98 // read tag 99 100 val s0_valid = io.lsu.req.fire() 101 val s0_req = io.lsu.req.bits 102 val s0_fire = s0_valid && s1_ready 103 val s0_vaddr = s0_req.addr 104 val s0_replayCarry = s0_req.replayCarry 105 assert(RegNext(!(s0_valid && (s0_req.cmd =/= MemoryOpConstants.M_XRD && s0_req.cmd =/= MemoryOpConstants.M_PFR && s0_req.cmd =/= MemoryOpConstants.M_PFW))), "LoadPipe only accepts load req / softprefetch read or write!") 106 dump_pipeline_reqs("LoadPipe s0", s0_valid, s0_req) 107 108 // -------------------------------------------------------------------------------- 109 // stage 1 110 // -------------------------------------------------------------------------------- 111 // tag match, read data 112 113 val s1_valid = RegInit(false.B) 114 val s1_req = RegEnable(s0_req, s0_fire) 115 // in stage 1, load unit gets the physical address 116 val s1_paddr_dup_lsu = io.lsu.s1_paddr_dup_lsu 117 val s1_paddr_dup_dcache = io.lsu.s1_paddr_dup_dcache 118 // LSU may update the address from io.lsu.s1_paddr, which affects the bank read enable only. 119 val s1_vaddr = Cat(s1_req.addr(PAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) 120 val s1_bank_oh = UIntToOH(addr_to_dcache_bank(s1_vaddr)) 121 val s1_nack = RegNext(io.nack) 122 val s1_nack_data = !io.banked_data_read.ready 123 val s1_fire = s1_valid && s2_ready 124 s1_ready := !s1_valid || s1_fire 125 126 when (s0_fire) { s1_valid := true.B } 127 .elsewhen (s1_fire) { s1_valid := false.B } 128 129 dump_pipeline_reqs("LoadPipe s1", s1_valid, s1_req) 130 131 // tag check 132 val meta_resp = io.meta_resp 133 val tag_resp = io.tag_resp.map(r => r(tagBits - 1, 0)) 134 def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) 135 136 // dcache side tag match 137 /* // just ideal situation 138 val idealWPU = Module(new IdealWPU) 139 val s1_vaddr_dup_dc = Wire(UInt(PAddrBits.W)) 140 s1_vaddr_dup_dc := RegEnable(s0_req.addr, s0_fire) 141 idealWPU.io.req.bits.vaddr := s1_vaddr_dup_dc 142 idealWPU.io.req.valid := true.B 143 idealWPU.io.idealIf.s1_tag_resp := tag_resp 144 idealWPU.io.idealIf.s1_meta_resp := meta_resp 145 idealWPU.io.idealIf.s1_real_tag := get_tag(s1_paddr_dup_dcache) 146 */ 147 // real wpu 148 val wpu = Module(new DCacheWPU) 149 // req in s0 150 wpu.io.req.bits.vaddr := s0_vaddr 151 wpu.io.req.bits.replayCarry := s0_replayCarry 152 wpu.io.req.valid := s0_valid 153 // check in s1 154 wpu.io.check.bits.s1_tag_resp := tag_resp 155 wpu.io.check.bits.s1_meta_resp := meta_resp 156 wpu.io.check.bits.s1_real_tag := get_tag(s1_paddr_dup_dcache) 157 wpu.io.check.valid := s1_valid 158 // correct in s2 159 val s2_wpu_pred_fail = wpu.io.s2_pred_fail 160 val s2_real_way_en = wpu.io.s2_real_way_en 161 162 // resp in s1 163 val s1_tag_match_way_dup_dc = Wire(UInt(nWays.W)) 164 val s1_tag_match_way_dup_lsu = Wire(UInt(nWays.W)) 165 when (wpu.io.resp.valid){ 166 s1_tag_match_way_dup_dc := wpu.io.resp.bits.predict_way_en 167 s1_tag_match_way_dup_lsu := wpu.io.resp.bits.predict_way_en 168 }.otherwise { 169 val s1_tag_eq_way_dup_dc = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_dcache))).asUInt 170 s1_tag_match_way_dup_dc := wayMap((w: Int) => s1_tag_eq_way_dup_dc(w) && meta_resp(w).coh.isValid()).asUInt 171 172 // lsu side tag match 173 val s1_tag_eq_way_dup_lsu = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_lsu))).asUInt 174 s1_tag_match_way_dup_lsu := wayMap((w: Int) => s1_tag_eq_way_dup_lsu(w) && meta_resp(w).coh.isValid()).asUInt 175 } 176 val s1_tag_match_dup_dc = s1_tag_match_way_dup_dc.orR 177 val s1_tag_match_dup_lsu = s1_tag_match_way_dup_lsu.orR 178 assert(RegNext(!s1_valid || PopCount(s1_tag_match_way_dup_dc) <= 1.U), "tag should not match with more than 1 way") 179 180 val s1_fake_meta = Wire(new Meta) 181// s1_fake_meta.tag := get_tag(s1_paddr_dup_dcache) 182 s1_fake_meta.coh := ClientMetadata.onReset 183 val s1_fake_tag = get_tag(s1_paddr_dup_dcache) 184 185 // when there are no tag match, we give it a Fake Meta 186 // this simplifies our logic in s2 stage 187 val s1_hit_meta = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => meta_resp(w))), s1_fake_meta) 188 val s1_hit_coh = s1_hit_meta.coh 189 val s1_hit_error = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).error)), false.B) 190 val s1_hit_prefetch = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).prefetch)), false.B) 191 val s1_hit_access = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).access)), false.B) 192 193 io.replace_way.set.valid := RegNext(s0_fire) 194 io.replace_way.set.bits := get_idx(s1_vaddr) 195 val s1_repl_way_en = UIntToOH(io.replace_way.way) 196 val s1_repl_tag = Mux1H(s1_repl_way_en, wayMap(w => tag_resp(w))) 197 val s1_repl_coh = Mux1H(s1_repl_way_en, wayMap(w => meta_resp(w).coh)) 198 val s1_repl_extra_meta = Mux1H(s1_repl_way_en, wayMap(w => io.extra_meta_resp(w))) 199 200 val s1_need_replacement = !s1_tag_match_dup_dc 201 val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way_dup_dc) 202 val s1_coh = Mux(s1_need_replacement, s1_repl_coh, s1_hit_coh) 203 val s1_tag = Mux(s1_need_replacement, s1_repl_tag, get_tag(s1_paddr_dup_dcache)) 204 205 // data read 206 io.banked_data_read.valid := s1_fire && !s1_nack 207 io.banked_data_read.bits.addr := s1_vaddr 208 io.banked_data_read.bits.way_en := s1_tag_match_way_dup_dc 209 210 // get s1_will_send_miss_req in lpad_s1 211 val s1_has_permission = s1_hit_coh.onAccess(s1_req.cmd)._1 212 val s1_new_hit_coh = s1_hit_coh.onAccess(s1_req.cmd)._3 213 val s1_hit = s1_tag_match_dup_dc && s1_has_permission && s1_hit_coh === s1_new_hit_coh 214 val s1_will_send_miss_req = s1_valid && !s1_nack && !s1_nack_data && !s1_hit 215 216 // check ecc error 217 val s1_encTag = Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.tag_resp(w))) 218 val s1_flag_error = Mux(s1_need_replacement, false.B, s1_hit_error) // error reported by exist dcache error bit 219 220 // -------------------------------------------------------------------------------- 221 // stage 2 222 // -------------------------------------------------------------------------------- 223 // return data 224 225 // val s2_valid = RegEnable(next = s1_valid && !io.lsu.s1_kill, init = false.B, enable = s1_fire) 226 val s2_valid = RegInit(false.B) 227 val s2_req = RegEnable(s1_req, s1_fire) 228 val s2_paddr = RegEnable(s1_paddr_dup_dcache, s1_fire) 229 val s2_vaddr = RegEnable(s1_vaddr, s1_fire) 230 val s2_bank_oh = RegEnable(s1_bank_oh, s1_fire) 231 val s2_bank_oh_dup_0 = RegEnable(s1_bank_oh, s1_fire) 232 s2_ready := true.B 233 234 val s2_fire = s2_valid 235 236 when (s1_fire) { s2_valid := !io.lsu.s1_kill } 237 .elsewhen(io.lsu.resp.fire()) { s2_valid := false.B } 238 239 dump_pipeline_reqs("LoadPipe s2", s2_valid, s2_req) 240 241 242 // hit, miss, nack, permission checking 243 // dcache side tag match 244 val s2_tag_match_way = RegEnable(s1_tag_match_way_dup_dc, s1_fire) 245 val s2_tag_match = RegEnable(s1_tag_match_dup_dc, s1_fire) 246 247 // lsu side tag match 248 val s2_hit_dup_lsu = RegNext(s1_tag_match_dup_lsu) 249 250 io.lsu.s2_hit := s2_hit_dup_lsu && !s2_wpu_pred_fail 251 252 val s2_hit_meta = RegEnable(s1_hit_meta, s1_fire) 253 val s2_hit_coh = RegEnable(s1_hit_coh, s1_fire) 254 val s2_has_permission = s2_hit_coh.onAccess(s2_req.cmd)._1 // for write prefetch 255 val s2_new_hit_coh = s2_hit_coh.onAccess(s2_req.cmd)._3 // for write prefetch 256 257 val s2_way_en = RegEnable(s1_way_en, s1_fire) 258 val s2_repl_coh = RegEnable(s1_repl_coh, s1_fire) 259 val s2_repl_tag = RegEnable(s1_repl_tag, s1_fire) 260 val s2_repl_extra_meta = RegEnable(s1_repl_extra_meta, s1_fire) // not used for now 261 val s2_encTag = RegEnable(s1_encTag, s1_fire) 262 263 // when req got nacked, upper levels should replay this request 264 // nacked or not 265 val s2_nack_hit = RegEnable(s1_nack, s1_fire) 266 // can no allocate mshr for load miss 267 val s2_nack_no_mshr = io.miss_req.valid && !io.miss_req.ready 268 // Bank conflict on data arrays 269 val s2_nack_data = RegEnable(!io.banked_data_read.ready, s1_fire) 270 val s2_nack = s2_nack_hit || s2_nack_no_mshr || s2_nack_data 271 272 val s2_bank_addr = addr_to_dcache_bank(s2_paddr) 273 dontTouch(s2_bank_addr) 274 275 val s2_instrtype = s2_req.instrtype 276 277 val s2_tag_error = dcacheParameters.tagCode.decode(s2_encTag).error // error reported by tag ecc check 278 val s2_flag_error = RegEnable(s1_flag_error, s1_fire) 279 280 val s2_hit_prefetch = RegEnable(s1_hit_prefetch, s1_fire) 281 val s2_hit_access = RegEnable(s1_hit_access, s1_fire) 282 283 val s2_hit = s2_tag_match && s2_has_permission && s2_hit_coh === s2_new_hit_coh && !s2_wpu_pred_fail 284 285 // only dump these signals when they are actually valid 286 dump_pipeline_valids("LoadPipe s2", "s2_hit", s2_valid && s2_hit) 287 dump_pipeline_valids("LoadPipe s2", "s2_nack", s2_valid && s2_nack) 288 dump_pipeline_valids("LoadPipe s2", "s2_nack_hit", s2_valid && s2_nack_hit) 289 dump_pipeline_valids("LoadPipe s2", "s2_nack_no_mshr", s2_valid && s2_nack_no_mshr) 290 291 val s2_can_send_miss_req = RegEnable(s1_will_send_miss_req, s1_fire) 292 293 // send load miss to miss queue 294 io.miss_req.valid := s2_valid && s2_can_send_miss_req && !s2_wpu_pred_fail 295 io.miss_req.bits := DontCare 296 io.miss_req.bits.source := s2_instrtype 297 io.miss_req.bits.cmd := s2_req.cmd 298 io.miss_req.bits.addr := get_block_addr(s2_paddr) 299 io.miss_req.bits.vaddr := s2_vaddr 300 io.miss_req.bits.way_en := s2_way_en 301 io.miss_req.bits.req_coh := s2_hit_coh 302 io.miss_req.bits.replace_coh := s2_repl_coh 303 io.miss_req.bits.replace_tag := s2_repl_tag 304 io.miss_req.bits.cancel := io.lsu.s2_kill || s2_tag_error 305 306 // send back response 307 val resp = Wire(ValidIO(new DCacheWordResp)) 308 resp.valid := s2_valid 309 resp.bits := DontCare 310 // resp.bits.data := s2_word_decoded 311 // resp.bits.data := banked_data_resp_word.raw_data 312 // * on miss or nack, upper level should replay request 313 // but if we successfully sent the request to miss queue 314 // upper level does not need to replay request 315 // they can sit in load queue and wait for refill 316 // 317 // * report a miss if bank conflict is detected 318 val real_miss = !s2_hit_dup_lsu 319 resp.bits.miss := real_miss || io.bank_conflict_slow || s2_wpu_pred_fail 320 // load pipe need replay when there is a bank conflict or wpu predict fail 321 resp.bits.replay := (resp.bits.miss && (!io.miss_req.fire() || s2_nack)) || io.bank_conflict_slow || s2_wpu_pred_fail 322 resp.bits.replayCarry.valid := resp.bits.miss 323 resp.bits.replayCarry.real_way_en := s2_real_way_en 324 resp.bits.meta_prefetch := s2_hit_prefetch 325 resp.bits.meta_access := s2_hit_access 326 resp.bits.tag_error := s2_tag_error // report tag_error in load s2 327 resp.bits.mshr_id := io.miss_resp.id 328 329 XSPerfAccumulate("wpu_pred_fail", s2_wpu_pred_fail && s2_valid) 330 XSPerfAccumulate("dcache_read_bank_conflict", io.bank_conflict_slow && s2_valid) 331 XSPerfAccumulate("dcache_read_from_prefetched_line", s2_valid && s2_hit_prefetch && !resp.bits.miss) 332 XSPerfAccumulate("dcache_first_read_from_prefetched_line", s2_valid && s2_hit_prefetch && !resp.bits.miss && !s2_hit_access) 333 334 io.lsu.resp.valid := resp.valid 335 io.lsu.resp.bits := resp.bits 336 assert(RegNext(!(resp.valid && !io.lsu.resp.ready)), "lsu should be ready in s2") 337 338 when (resp.valid) { 339 resp.bits.dump() 340 } 341 342 io.lsu.debug_s1_hit_way := s1_tag_match_way_dup_dc 343 io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup 344 io.lsu.s1_bank_conflict := io.bank_conflict_fast 345 assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked") 346 347 // -------------------------------------------------------------------------------- 348 // stage 3 349 // -------------------------------------------------------------------------------- 350 // report ecc error and get selected dcache data 351 352 val s3_valid = RegNext(s2_valid) 353 val s3_vaddr = RegEnable(s2_vaddr, s2_fire) 354 val s3_paddr = RegEnable(s2_paddr, s2_fire) 355 val s3_hit = RegEnable(s2_hit, s2_fire) 356 val s3_tag_match_way = RegEnable(s2_tag_match_way, s2_fire) 357 358 val s3_banked_data_resp_word = io.banked_data_resp.raw_data 359 val s3_data_error = io.read_error_delayed // banked_data_resp_word.error && !bank_conflict 360 val s3_tag_error = RegEnable(s2_tag_error, s2_fire) 361 val s3_flag_error = RegEnable(s2_flag_error, s2_fire) 362 val s3_error = s3_tag_error || s3_flag_error || s3_data_error 363 364 // error_delayed signal will be used to update uop.exception 1 cycle after load writeback 365 resp.bits.error_delayed := s3_error && (s3_hit || s3_tag_error) && s3_valid 366 resp.bits.data_delayed := s3_banked_data_resp_word 367 368 // report tag / data / l2 error (with paddr) to bus error unit 369 io.error := 0.U.asTypeOf(new L1CacheErrorInfo()) 370 io.error.report_to_beu := (s3_tag_error || s3_data_error) && s3_valid 371 io.error.paddr := s3_paddr 372 io.error.source.tag := s3_tag_error 373 io.error.source.data := s3_data_error 374 io.error.source.l2 := s3_flag_error 375 io.error.opType.load := true.B 376 // report tag error / l2 corrupted to CACHE_ERROR csr 377 io.error.valid := s3_error && s3_valid 378 379 // update plru in s3 380 io.replace_access.valid := RegNext(RegNext(RegNext(io.meta_read.fire()) && s1_valid && !io.lsu.s1_kill) && !s2_nack_no_mshr) 381 io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr))) 382 io.replace_access.bits.way := RegNext(RegNext(Mux(s1_tag_match_dup_dc, OHToUInt(s1_tag_match_way_dup_dc), io.replace_way.way))) 383 384 // update access bit 385 io.access_flag_write.valid := s3_valid && s3_hit 386 io.access_flag_write.bits.idx := get_idx(s3_vaddr) 387 io.access_flag_write.bits.way_en := s3_tag_match_way 388 io.access_flag_write.bits.flag := true.B 389 390 // -------------------------------------------------------------------------------- 391 // Debug logging functions 392 def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool, 393 req: DCacheWordReq ) = { 394 when (valid) { 395 XSDebug(s"$pipeline_stage_name: ") 396 req.dump() 397 } 398 } 399 400 def dump_pipeline_valids(pipeline_stage_name: String, signal_name: String, valid: Bool) = { 401 when (valid) { 402 XSDebug(s"$pipeline_stage_name $signal_name\n") 403 } 404 } 405 406 // performance counters 407 XSPerfAccumulate("load_req", io.lsu.req.fire()) 408 XSPerfAccumulate("load_s1_kill", s1_fire && io.lsu.s1_kill) 409 XSPerfAccumulate("load_hit_way", s1_fire && s1_tag_match_dup_dc) 410 XSPerfAccumulate("load_replay", io.lsu.resp.fire() && resp.bits.replay) 411 XSPerfAccumulate("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data) 412 XSPerfAccumulate("load_replay_for_no_mshr", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr) 413 XSPerfAccumulate("load_replay_for_conflict", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow) 414 XSPerfAccumulate("load_hit", io.lsu.resp.fire() && !real_miss) 415 XSPerfAccumulate("load_miss", io.lsu.resp.fire() && real_miss) 416 XSPerfAccumulate("load_succeed", io.lsu.resp.fire() && !resp.bits.miss && !resp.bits.replay) 417 XSPerfAccumulate("load_miss_or_conflict", io.lsu.resp.fire() && resp.bits.miss) 418 XSPerfAccumulate("actual_ld_fast_wakeup", s1_fire && s1_tag_match_dup_dc && !io.disable_ld_fast_wakeup) 419 XSPerfAccumulate("ideal_ld_fast_wakeup", io.banked_data_read.fire() && s1_tag_match_dup_dc) 420 421 val perfEvents = Seq( 422 ("load_req ", io.lsu.req.fire() ), 423 ("load_replay ", io.lsu.resp.fire() && resp.bits.replay ), 424 ("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data ), 425 ("load_replay_for_no_mshr ", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr ), 426 ("load_replay_for_conflict ", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow ), 427 ) 428 generatePerfEvent() 429} 430