1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes} 25import freechips.rocketchip.tilelink._ 26import device.RAMHelper 27 28class FakeDCache()(implicit p: Parameters) extends XSModule with HasDCacheParameters { 29 val io = IO(new DCacheIO) 30 31 io := DontCare 32 // to LoadUnit 33 for (i <- 0 until LoadPipelineWidth) { 34 val fakeRAM = Module(new RAMHelper(64L * 1024 * 1024 * 1024)) 35 fakeRAM.clk := clock 36 fakeRAM.en := io.lsu.load(i).resp.valid && !reset.asBool 37 fakeRAM.rIdx := RegNext((io.lsu.load(i).s1_paddr - "h80000000".U) >> 3) 38 fakeRAM.wIdx := 0.U 39 fakeRAM.wdata := 0.U 40 fakeRAM.wmask := 0.U 41 fakeRAM.wen := false.B 42 43 io.lsu.load(i).req.ready := true.B 44 io.lsu.load(i).resp.valid := RegNext(RegNext(io.lsu.load(i).req.valid) && !io.lsu.load(i).s1_kill) 45 io.lsu.load(i).resp.bits.data := fakeRAM.rdata 46 io.lsu.load(i).resp.bits.miss := false.B 47 io.lsu.load(i).resp.bits.replay := false.B 48 io.lsu.load(i).resp.bits.id := DontCare 49 io.lsu.load(i).s1_hit_way := 1.U 50 io.lsu.load(i).s1_disable_fast_wakeup := false.B 51 } 52 // to LSQ 53 io.lsu.lsq.valid := false.B 54 io.lsu.lsq.bits := DontCare 55 // to Store Buffer 56 io.lsu.store.req.ready := true.B 57 io.lsu.store.main_pipe_hit_resp := DontCare 58 io.lsu.store.refill_hit_resp := DontCare 59 io.lsu.store.replay_resp := DontCare 60 io.lsu.store.main_pipe_hit_resp.valid := RegNext(io.lsu.store.req.valid) 61 io.lsu.store.main_pipe_hit_resp.bits.id := RegNext(io.lsu.store.req.bits.id) 62 // to atomics 63 val amoHelper = Module(new AMOHelper) 64 amoHelper.clock := clock 65 amoHelper.enable := io.lsu.atomics.req.valid && !reset.asBool 66 amoHelper.cmd := io.lsu.atomics.req.bits.cmd 67 amoHelper.addr := io.lsu.atomics.req.bits.addr 68 amoHelper.wdata := io.lsu.atomics.req.bits.data 69 amoHelper.mask := io.lsu.atomics.req.bits.mask 70 io.lsu.atomics.req.ready := true.B 71 io.lsu.atomics.resp.valid := RegNext(io.lsu.atomics.req.valid) 72 assert(!io.lsu.atomics.resp.valid || io.lsu.atomics.resp.ready) 73 io.lsu.atomics.resp.bits.data := amoHelper.rdata 74 io.lsu.atomics.resp.bits.replay := false.B 75 io.lsu.atomics.resp.bits.id := 1.U 76}