1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chisel3._ 20import difftest.common.DifftestMem 21import org.chipsalliance.cde.config.Parameters 22import xiangshan._ 23 24class FakeDCache()(implicit p: Parameters) extends XSModule with HasDCacheParameters { 25 val io = IO(new DCacheIO) 26 27 io := DontCare 28 // to LoadUnit 29 for (i <- 0 until LoadPipelineWidth) { 30 val ram = DifftestMem(64L * 1024 * 1024 * 1024, 8) 31 val ren = RegNext(io.lsu.load(i).req.valid) 32 val raddr = ((io.lsu.load(i).s1_paddr_dup_dcache - "h80000000".U) >> 3).asUInt 33 34 io.lsu.load(i).req.ready := true.B 35 io.lsu.load(i).resp.valid := RegNext(ren && !io.lsu.load(i).s1_kill) 36 io.lsu.load(i).resp.bits.data := ram.readAndHold(raddr, ren) 37 io.lsu.load(i).resp.bits.miss := false.B 38 io.lsu.load(i).resp.bits.replay := false.B 39 io.lsu.load(i).resp.bits.id := DontCare 40 io.lsu.load(i).s2_hit := true.B 41 io.lsu.load(i).s1_disable_fast_wakeup := false.B 42 } 43 // to LSQ 44 io.lsu.lsq.valid := false.B 45 io.lsu.lsq.bits := DontCare 46 // to Store Buffer 47 io.lsu.store.req.ready := true.B 48 io.lsu.store.main_pipe_hit_resp := DontCare 49 io.lsu.store.refill_hit_resp := DontCare 50 io.lsu.store.replay_resp := DontCare 51 io.lsu.store.main_pipe_hit_resp.valid := RegNext(io.lsu.store.req.valid) 52 io.lsu.store.main_pipe_hit_resp.bits.id := RegNext(io.lsu.store.req.bits.id) 53 // to atomics 54 val amoHelper = Module(new AMOHelper) 55 amoHelper.clock := clock 56 amoHelper.enable := io.lsu.atomics.req.valid && !reset.asBool 57 amoHelper.cmd := io.lsu.atomics.req.bits.cmd 58 amoHelper.addr := io.lsu.atomics.req.bits.addr 59 amoHelper.wdata := io.lsu.atomics.req.bits.amo_data 60 amoHelper.mask := io.lsu.atomics.req.bits.amo_mask 61 io.lsu.atomics.req.ready := true.B 62 io.lsu.atomics.resp.valid := RegNext(io.lsu.atomics.req.valid) 63 // assert(!io.lsu.atomics.resp.valid || io.lsu.atomics.resp.ready) 64 io.lsu.atomics.resp.bits.data := amoHelper.rdata 65 io.lsu.atomics.resp.bits.replay := false.B 66 io.lsu.atomics.resp.bits.id := 1.U 67}