1// See LICENSE.SiFive for license details. 2 3package xiangshan.cache 4 5import chisel3._ 6import chisel3.util._ 7import xiangshan.{HasXSParameter, XSBundle, XSModule} 8 9// this file contains common building blocks that can be shared by ICache and DCache 10// this is the common parameter base for L1 ICache and L1 DCache 11trait L1CacheParameters { 12 def nSets: Int 13 def nWays: Int 14 def rowBits: Int 15 def blockBytes: Int 16} 17 18trait HasL1CacheParameters extends HasXSParameter 19 with MemoryOpConstants { 20 val cacheParams: L1CacheParameters 21 22 def nSets = cacheParams.nSets 23 def nWays = cacheParams.nWays 24 def blockBytes = cacheParams.blockBytes 25 26 def idxBits = log2Up(cacheParams.nSets) 27 def wayBits = log2Up(nWays) 28 def blockOffBits = log2Up(cacheParams.blockBytes) 29 30 def untagBits = blockOffBits + idxBits 31 // 4K page 32 def pgIdxBits = 12 33 def pgUntagBits = untagBits min pgIdxBits 34 def tagBits = PAddrBits - pgUntagBits 35 36 // the basic unit at which we store contents 37 // SRAM bank width 38 def rowBits = cacheParams.rowBits 39 def rowBytes = rowBits/8 40 def rowOffBits = log2Up(rowBytes) 41 // the number of rows in a block 42 def blockRows = blockBytes / rowBytes 43 44 // outer bus width 45 def beatBits = l1BusDataWidth 46 def beatBytes = beatBits / 8 47 def refillCycles = blockBytes / beatBytes 48 def beatOffBits = log2Up(beatBytes) 49 50 // inner bus width(determined by XLEN) 51 def wordBits = DataBits 52 def wordBytes = wordBits / 8 53 def wordOffBits = log2Up(wordBytes) 54 // the number of words in a block 55 def blockWords = blockBytes / wordBytes 56 57 def idxMSB = untagBits-1 58 def idxLSB = blockOffBits 59 def offsetmsb = idxLSB-1 60 def offsetlsb = wordOffBits 61 62 def get_tag(addr: UInt) = (addr >> untagBits).asUInt() 63 def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) 64 def get_block(addr: UInt) = addr >> blockOffBits 65 def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits 66 67 def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits) 68 def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits) 69 def get_word(addr: UInt) = addr(blockOffBits - 1, wordOffBits) 70 71 def beatRows = beatBits/rowBits 72 def rowWords = rowBits/wordBits 73 74 def full_divide(a: Int, b: Int) = a >= b && isPow2(a / b) 75} 76 77abstract class L1CacheModule extends XSModule 78 with HasL1CacheParameters 79 80abstract class L1CacheBundle extends XSBundle 81 with HasL1CacheParameters 82