1// See LICENSE.SiFive for license details. 2 3package xiangshan.cache 4 5import chisel3._ 6import chisel3.util._ 7import xiangshan.{HasXSParameter, XSBundle, XSModule} 8 9// this file contains common building blocks that can be shared by ICache and DCache 10// this is the common parameter base for L1 ICache and L1 DCache 11trait L1CacheParameters { 12 def nSets: Int 13 def nWays: Int 14 def rowBits: Int 15 def blockBytes: Int 16} 17 18trait HasL1CacheParameters extends HasXSParameter 19 with MemoryOpConstants { 20 val cacheParams: L1CacheParameters 21 22 def nSets = cacheParams.nSets 23 def nWays = cacheParams.nWays 24 def blockBytes = cacheParams.blockBytes 25 def blockBits = blockBytes * 8 26 27 def idxBits = log2Up(cacheParams.nSets) 28 def wayBits = log2Up(nWays) 29 def blockOffBits = log2Up(cacheParams.blockBytes) 30 31 def untagBits = blockOffBits + idxBits 32 // 4K page 33 def pgIdxBits = 12 34 def pgUntagBits = untagBits min pgIdxBits 35 def tagBits = PAddrBits - pgUntagBits 36 37 // the basic unit at which we store contents 38 // SRAM bank width 39 def rowBits = cacheParams.rowBits 40 def rowBytes = rowBits/8 41 def rowOffBits = log2Up(rowBytes) 42 // the number of rows in a block 43 def blockRows = blockBytes / rowBytes 44 45 // outer bus width 46 def beatBits = l1BusDataWidth 47 def beatBytes = beatBits / 8 48 def refillCycles = blockBytes / beatBytes 49 def beatOffBits = log2Up(beatBytes) 50 51 // inner bus width(determined by XLEN) 52 def wordBits = DataBits 53 def wordBytes = wordBits / 8 54 def wordOffBits = log2Up(wordBytes) 55 // the number of words in a block 56 def blockWords = blockBytes / wordBytes 57 58 def idxMSB = untagBits-1 59 def idxLSB = blockOffBits 60 def offsetmsb = idxLSB-1 61 def offsetlsb = wordOffBits 62 63 def get_tag(addr: UInt) = (addr >> untagBits).asUInt() 64 def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) 65 def get_block(addr: UInt) = addr >> blockOffBits 66 def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits 67 68 def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits) 69 def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits) 70 def get_word(addr: UInt) = addr(blockOffBits - 1, wordOffBits) 71 72 def beatRows = beatBits/rowBits 73 def rowWords = rowBits/wordBits 74 75 def full_divide(a: Int, b: Int) = a >= b && isPow2(a / b) 76} 77 78abstract class L1CacheModule extends XSModule 79 with HasL1CacheParameters 80 81abstract class L1CacheBundle extends XSBundle 82 with HasL1CacheParameters 83