1// See LICENSE.SiFive for license details. 2 3package xiangshan.cache 4 5import chisel3._ 6import chisel3.util._ 7import xiangshan.{HasXSParameter, XSBundle, XSModule} 8 9// this file contains common building blocks that can be shared by ICache and DCache 10// this is the common parameter base for L1 ICache and L1 DCache 11trait L1CacheParameters { 12 def nSets: Int 13 def nWays: Int 14 def rowBits: Int 15 def nTLBEntries: Int 16 def blockBytes: Int 17} 18 19trait HasL1CacheParameters extends HasXSParameter 20 with MemoryOpConstants { 21 val cacheParams: L1CacheParameters 22 23 def nSets = cacheParams.nSets 24 def blockOffBits = log2Up(cacheParams.blockBytes) 25 def idxBits = log2Up(cacheParams.nSets) 26 def untagBits = blockOffBits + idxBits 27 // 4K page 28 def pgIdxBits = 12 29 def pgUntagBits = untagBits min pgIdxBits 30 31 // L1 cache are all physically tagged cache 32 def tagBits = PAddrBits - pgUntagBits 33 def nWays = cacheParams.nWays 34 def wayBits = log2Up(nWays) 35 def rowBits = cacheParams.rowBits 36 def rowBytes = rowBits/8 37 def rowOffBits = log2Up(rowBytes) 38 def nTLBEntries = cacheParams.nTLBEntries 39 40 def cacheDataBits = l1BusDataWidth 41 def cacheDataBytes = cacheDataBits / 8 42 def cacheDataBeats = (cacheParams.blockBytes * 8) / cacheDataBits 43 def refillCycles = cacheDataBeats 44} 45 46abstract class L1CacheModule extends XSModule 47 with HasL1CacheParameters 48 49abstract class L1CacheBundle extends XSBundle 50 with HasL1CacheParameters 51