1// See LICENSE.SiFive for license details. 2 3package xiangshan.cache 4 5import chisel3._ 6import chisel3.util._ 7 8import xiangshan.{HasXSParameter, XSModule, XSBundle} 9 10// this file contains common building blocks that can be shared by ICache and DCache 11// this is the common parameter base for L1 ICache and L1 DCache 12trait L1CacheParameters { 13 def nSets: Int 14 def nWays: Int 15 def rowBits: Int 16 def nTLBEntries: Int 17 def blockBytes: Int 18} 19 20trait HasL1CacheParameters extends HasXSParameter 21 with MemoryOpConstants { 22 val cacheParams: L1CacheParameters 23 24 def nSets = cacheParams.nSets 25 def blockOffBits = log2Up(cacheParams.blockBytes) 26 def idxBits = log2Up(cacheParams.nSets) 27 def untagBits = blockOffBits + idxBits 28 // 4K page 29 def pgIdxBits = 12 30 def pgUntagBits = untagBits min pgIdxBits 31 32 // L1 cache are all physically tagged cache 33 def tagBits = PAddrBits - pgUntagBits 34 def nWays = cacheParams.nWays 35 def wayBits = log2Up(nWays) 36 def rowBits = cacheParams.rowBits 37 def rowBytes = rowBits/8 38 def rowOffBits = log2Up(rowBytes) 39 def nTLBEntries = cacheParams.nTLBEntries 40 41 def cacheDataBits = l1BusDataWidth 42 def cacheDataBytes = cacheDataBits / 8 43 def cacheDataBeats = (cacheParams.blockBytes * 8) / cacheDataBits 44 def refillCycles = cacheDataBeats 45} 46 47abstract class L1CacheModule extends XSModule 48 with HasL1CacheParameters 49 50abstract class L1CacheBundle extends XSBundle 51 with HasL1CacheParameters 52