1package xiangshan.cache 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.frontend._ 7import utils._ 8import chipsalliance.rocketchip.config.Parameters 9 10object CacheOpMap{ 11 def apply(opcode: String, optype: String, name: String ): Map[String, String] = { 12 Map( 13 "opcode" -> opcode, 14 "optype" -> optype, 15 "name" -> name, 16 ) 17 } 18} 19 20object CacheRegMap{ 21 def apply(offset: String, width: String, authority: String, name: String ): Pair[String, Map[String, String]] = { 22 name -> Map( 23 "offset" -> offset, 24 "width" -> width, 25 "authority" -> authority, 26 ) 27 } 28} 29 30trait CacheControlConst{ 31 def maxDataRowSupport = 8 32} 33 34object CacheInstrucion{ 35 def CacheOperation = List( 36 CacheOpMap("b00000", "CHECK", "READ_TAG_ECC"), 37 CacheOpMap("b00001", "CHECK", "READ_DATA_ECC"), 38 CacheOpMap("b00010", "LOAD", "READ_TAG"), 39 CacheOpMap("b00011", "LOAD", "READ_DATA"), 40 CacheOpMap("b00100", "STORE", "WRITE_TAG_ECC"), 41 CacheOpMap("b00101", "STORE", "WRITE_DATA_ECC"), 42 CacheOpMap("b00110", "STORE", "WRITE_TAG"), 43 CacheOpMap("b00111", "STORE", "WRITE_DATA"), 44 CacheOpMap("b01000", "FLUSH", "FLUSH_BLOCK") 45 ) 46 47 def CacheInsRegisterList = Map( 48 /** offset width authority name */ 49 CacheRegMap("0", "64", "RW", "CACHE_LEVEL"), 50 CacheRegMap("1", "64", "RW", "CACHE_WAY"), 51 CacheRegMap("2", "64", "RW", "CACHE_IDX"), 52 CacheRegMap("3", "64", "RW", "CACHE_TAG_ECC"), 53 CacheRegMap("4", "64", "RW", "CACHE_TAG_BITS"), 54 CacheRegMap("5", "64", "RW", "CACHE_TAG_LOW"), 55 CacheRegMap("6", "64", "RW", "CACHE_TAG_HIGH"), 56 CacheRegMap("7", "64", "R", "CACHE_ECC_WIDTH"), 57 CacheRegMap("8", "64", "RW", "CACHE_ECC_NUM"), 58 CacheRegMap("9", "64", "RW", "CACHE_DATA_ECC"), 59 CacheRegMap("10", "64", "RW", "CACHE_DATA_0"), 60 CacheRegMap("11", "64", "RW", "CACHE_DATA_1"), 61 CacheRegMap("12", "64", "RW", "CACHE_DATA_2"), 62 CacheRegMap("13", "64", "RW", "CACHE_DATA_3"), 63 CacheRegMap("14", "64", "RW", "CACHE_DATA_4"), 64 CacheRegMap("15", "64", "RW", "CACHE_DATA_5"), 65 CacheRegMap("16", "64", "RW", "CACHE_DATA_6"), 66 CacheRegMap("17", "64", "RW", "CACHE_DATA_7"), 67 CacheRegMap("18", "64", "R", "OP_FINISH") , 68 CacheRegMap("19", "64", "RW", "CACHE_OP") 69 ) 70 71 def COP_CHECK = 0.U 72 def COP_LOAD = 1.U 73 def COP_STORE = 2.U 74 def COP_FLUSH = 3.U 75 76 def isReadTagECC(opcode: UInt) = opcode === "b00000".U 77 def isReadDataECC(opcode: UInt) = opcode === "b00001".U 78 def isReadTag(opcode: UInt) = opcode === "b00010".U 79 def isReadData(opcode: UInt) = opcode === "b00011".U 80 def isWriteTagECC(opcode: UInt) = opcode === "b00101".U 81 def isWriteTag(opcode: UInt) = opcode === "b00110".U 82 def isWriteData(opcode: UInt) = opcode === "b00111".U 83 def isFlush(opcode: UInt) = opcode === "b01000".U 84} 85 86class CacheCtrlReqInfo(implicit p: Parameters) extends XSBundle with CacheControlConst { 87 val wayNum = UInt(XLEN.W) 88 val index = UInt(XLEN.W) 89 val opCode = UInt(XLEN.W) 90 val write_tag_high = UInt(XLEN.W) 91 val write_tag_low = UInt(XLEN.W) 92 val write_tag_ecc = UInt(XLEN.W) 93 val write_data_vec = Vec(maxDataRowSupport, UInt(XLEN.W)) 94 val write_data_ecc = UInt(XLEN.W) 95 val ecc_num = UInt(XLEN.W) 96} 97 98class CacheCtrlRespInfo(implicit p: Parameters) extends XSBundle with HasICacheParameters with CacheControlConst{ 99 val read_tag_high = UInt(XLEN.W) 100 val read_tag_low = UInt(XLEN.W) 101 val read_tag_ecc = UInt(XLEN.W) 102 val read_data_vec = Vec(maxDataRowSupport, UInt(XLEN.W)) 103 val read_data_ecc = UInt(XLEN.W) 104 val ecc_num = UInt(XLEN.W) 105} 106 107 108// class CSRCacheInsIO(implicit p: Parameters) extends XSModule{ 109// // TODO: extend pmp cfg interface 110// } 111