xref: /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala (revision 57bb43b5f11c3f1e89ac52f232fe73056b35d9bd) 
1package xiangshan.cache
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.frontend.icache._
7import utils._
8import chipsalliance.rocketchip.config.Parameters
9import xiangshan.backend.fu.util.HasCSRConst
10
11object CacheOpMap{
12  def apply(opcode: String, optype: String,  name: String ): Map[String, String] = {
13    Map(
14      "opcode" -> opcode,
15      "optype" -> optype,
16      "name"   -> name,
17    )
18  }
19}
20
21object CacheRegMap{
22  def apply(offset: String,  width: String, authority: String, name: String ): Pair[String, Map[String, String]] = {
23    name -> Map(
24      "offset" -> offset,
25      "width"  -> width,
26      "authority" -> authority,
27    )
28  }
29}
30
31trait CacheControlConst{
32  def maxDataRowSupport = 8
33}
34
35abstract class CacheCtrlModule(implicit p: Parameters) extends XSModule with HasCSRConst with CacheControlConst
36
37object CacheInstrucion{
38  def CacheOperation = List(
39    CacheOpMap("b00000", "CHECK",  "READ_TAG_ECC"),
40    CacheOpMap("b00001", "CHECK",  "READ_DATA_ECC"),
41    CacheOpMap("b00010", "LOAD",   "READ_TAG"),
42    CacheOpMap("b00011", "LOAD",   "READ_DATA"),
43    CacheOpMap("b00100", "STORE",  "WRITE_TAG_ECC"),
44    CacheOpMap("b00101", "STORE",  "WRITE_DATA_ECC"),
45    CacheOpMap("b00110", "STORE",  "WRITE_TAG"),
46    CacheOpMap("b00111", "STORE",  "WRITE_DATA"),
47    CacheOpMap("b01000", "FLUSH",  "FLUSH_BLOCK")
48  )
49
50  def CacheInsRegisterList = Map(
51    //         offset     width    authority  name
52    CacheRegMap("0",      "64",    "RW",      "CACHE_OP"),
53    CacheRegMap("1",      "64",    "RW",      "OP_FINISH"),
54    CacheRegMap("2",      "64",    "RW",      "CACHE_LEVEL"),
55    CacheRegMap("3",      "64",    "RW",      "CACHE_WAY"),
56    CacheRegMap("4",      "64",    "RW",      "CACHE_IDX"),
57    CacheRegMap("5",      "64",    "RW",      "CACHE_BANK_NUM"),
58    CacheRegMap("6",      "64",    "RW",      "CACHE_TAG_ECC"),
59    CacheRegMap("7",      "64",    "RW",      "CACHE_TAG_BITS"), // TODO
60    CacheRegMap("8",      "64",    "RW",      "CACHE_TAG_LOW"),
61    CacheRegMap("9",      "64",    "RW",      "CACHE_TAG_HIGH"), // not used in 64 bit arch
62    CacheRegMap("10",     "64",    "RW",      "CACHE_ECC_WIDTH"), // TODO
63    CacheRegMap("11",     "64",    "RW",      "CACHE_DATA_ECC"),
64    CacheRegMap("12",     "64",    "RW",      "CACHE_DATA_0"),
65    CacheRegMap("13",     "64",    "RW",      "CACHE_DATA_1"),
66    CacheRegMap("14",     "64",    "RW",      "CACHE_DATA_2"),
67    CacheRegMap("15",     "64",    "RW",      "CACHE_DATA_3"),
68    CacheRegMap("16",     "64",    "RW",      "CACHE_DATA_4"),
69    CacheRegMap("17",     "64",    "RW",      "CACHE_DATA_5"),
70    CacheRegMap("18",     "64",    "RW",      "CACHE_DATA_6"),
71    CacheRegMap("19",     "64",    "RW",      "CACHE_DATA_7"),
72    CacheRegMap("20",     "64",    "RW",      "CACHE_ERROR"),
73  )
74
75  // Usage:
76  // val cacheopMapping = CacheInstrucion.CacheInsRegisterList.map{case (name, attribute) => {
77  //   doSthWith(name, attribute("offset"), attribute("width"))
78  // }}
79
80  def COP_CHECK = 0.U
81  def COP_LOAD  = 1.U
82  def COP_STORE = 2.U
83  def COP_FLUSH = 3.U
84
85  def COP_ID_ICACHE = 0
86  def COP_ID_DCACHE = 1
87
88  def COP_RESULT_CODE_IDLE = 0.U
89  def COP_RESULT_CODE_OK = 1.U
90  def COP_RESULT_CODE_ERROR = 2.U
91
92  def isReadTagECC(opcode: UInt)            = opcode === "b00000".U
93  def isReadDataECC(opcode: UInt)           = opcode === "b00001".U
94  def isReadTag(opcode: UInt)               = opcode === "b00010".U
95  def isReadData(opcode: UInt)              = opcode === "b00011".U
96  def isWriteTagECC(opcode: UInt)           = opcode === "b00100".U
97  def isWriteDataECC(opcode: UInt)          = opcode === "b00101".U
98  def isWriteTag(opcode: UInt)              = opcode === "b00110".U
99  def isWriteData(opcode: UInt)             = opcode === "b00111".U
100  def isFlush(opcode: UInt)                 = opcode === "b01000".U
101
102  def isReadOp(opcode: UInt) = isReadTagECC(opcode) ||
103    isReadDataECC(opcode) ||
104    isReadTag(opcode) ||
105    isReadData(opcode)
106}
107
108class CacheCtrlReqInfo(implicit p: Parameters) extends XSBundle with CacheControlConst {
109  val level           = UInt(XLEN.W) // op target id
110  val wayNum          = UInt(XLEN.W)
111  val index           = UInt(XLEN.W)
112  val opCode          = UInt(XLEN.W)
113  val write_tag_high  = UInt(XLEN.W)
114  val write_tag_low   = UInt(XLEN.W)
115  val write_tag_ecc   = UInt(XLEN.W)
116  val write_data_vec  = Vec(maxDataRowSupport, UInt(XLEN.W))
117  val write_data_ecc  = UInt(XLEN.W)
118  val bank_num         = UInt(XLEN.W)
119}
120
121class CacheCtrlRespInfo(implicit p: Parameters) extends XSBundle with HasICacheParameters with CacheControlConst{
122  val read_tag_high  = UInt(XLEN.W)
123  val read_tag_low   = UInt(XLEN.W)
124  val read_tag_ecc   = UInt(XLEN.W)
125  val read_data_vec  = Vec(maxDataRowSupport, UInt(XLEN.W))
126  val read_data_ecc  = UInt(XLEN.W)
127  val bank_num        = UInt(XLEN.W)
128}
129
130class L1CacheToCsrIO(implicit p: Parameters) extends DCacheBundle {
131  val distribute_csr = Flipped(new DistributedCSRIO)
132  val update = new DistributedCSRUpdateReq
133}
134
135class L1CacheInnerOpIO(implicit p: Parameters) extends DCacheBundle {
136  val req  = Valid(new CacheCtrlReqInfo)
137  val resp = Flipped(Valid(new CacheCtrlRespInfo))
138}
139
140class CSRCacheOpDecoder(decoder_name: String, id: Int)(implicit p: Parameters) extends CacheCtrlModule {
141  val io = IO(new Bundle {
142    val csr = new L1CacheToCsrIO
143    val cache = new L1CacheInnerOpIO
144    val error = Flipped(new L1CacheErrorInfo)
145  })
146
147  // CSRCacheOpDecoder state
148  val wait_csr_op_req = RegInit(true.B) // waiting for csr "CACHE_OP" being write
149  val wait_cache_op_resp = RegInit(false.B) // waiting for dcache to finish dcache op
150  val schedule_csr_op_resp_data = RegInit(false.B) // ready to write data readed from cache back to csr
151  val schedule_csr_op_resp_finish = RegInit(false.B) // ready to write "OP_FINISH" csr
152  // val cache_op_resp_timer = RegInit(0.U(4.W))
153  val data_transfer_finished = WireInit(false.B)
154  val data_transfer_cnt = RegInit(0.U(log2Up(maxDataRowSupport).W))
155
156  // Translate CSR write to cache op
157  val translated_cache_req = Reg(new CacheCtrlReqInfo)
158  println("Cache op decoder (" + decoder_name + "):")
159  println("  Id " + id)
160  // CacheInsRegisterList.map{case (name, attribute) => {
161  //   println("  Register CSR mirror " + name)
162  // }}
163
164  def cacheop_csr_is_being_write(csr_name: String): Bool = {
165    io.csr.distribute_csr.w.bits.addr === (CacheInstrucion.CacheInsRegisterList(csr_name)("offset").toInt + Scachebase).U &&
166      io.csr.distribute_csr.w.valid
167  }
168
169  def update_cache_req_when_write(csr_name: String, req_field: Data) = {
170    when(
171      cacheop_csr_is_being_write(csr_name)
172    ){
173      req_field := io.csr.distribute_csr.w.bits.data
174      assert(wait_csr_op_req)
175    }
176  }
177
178  update_cache_req_when_write("CACHE_OP", translated_cache_req.opCode)
179  update_cache_req_when_write("CACHE_LEVEL", translated_cache_req.level)
180  update_cache_req_when_write("CACHE_WAY", translated_cache_req.wayNum)
181  update_cache_req_when_write("CACHE_IDX", translated_cache_req.index)
182  update_cache_req_when_write("CACHE_BANK_NUM", translated_cache_req.bank_num)
183  update_cache_req_when_write("CACHE_TAG_HIGH", translated_cache_req.write_tag_high)
184  update_cache_req_when_write("CACHE_TAG_LOW", translated_cache_req.write_tag_low)
185  update_cache_req_when_write("CACHE_TAG_ECC", translated_cache_req.write_tag_ecc)
186  update_cache_req_when_write("CACHE_DATA_0", translated_cache_req.write_data_vec(0))
187  update_cache_req_when_write("CACHE_DATA_1", translated_cache_req.write_data_vec(1))
188  update_cache_req_when_write("CACHE_DATA_2", translated_cache_req.write_data_vec(2))
189  update_cache_req_when_write("CACHE_DATA_3", translated_cache_req.write_data_vec(3))
190  update_cache_req_when_write("CACHE_DATA_4", translated_cache_req.write_data_vec(4))
191  update_cache_req_when_write("CACHE_DATA_5", translated_cache_req.write_data_vec(5))
192  update_cache_req_when_write("CACHE_DATA_6", translated_cache_req.write_data_vec(6))
193  update_cache_req_when_write("CACHE_DATA_7", translated_cache_req.write_data_vec(7))
194  update_cache_req_when_write("CACHE_DATA_ECC", translated_cache_req.write_data_ecc)
195
196  val cache_op_start = WireInit(cacheop_csr_is_being_write("CACHE_OP") && id.U === translated_cache_req.level)
197  when(cache_op_start) {
198    wait_csr_op_req := false.B
199  }
200
201  // Send cache op to cache
202  io.cache.req.valid := RegNext(cache_op_start)
203  io.cache.req.bits := translated_cache_req
204  when(io.cache.req.fire()){
205    wait_cache_op_resp := true.B
206  }
207
208  // Receive cache op resp from cache
209  val raw_cache_resp = Reg(new CacheCtrlRespInfo)
210  when(io.cache.resp.fire()){
211    wait_cache_op_resp := false.B
212    raw_cache_resp := io.cache.resp.bits
213    when(CacheInstrucion.isReadOp(translated_cache_req.opCode)){
214      schedule_csr_op_resp_data := true.B
215      schedule_csr_op_resp_finish := false.B
216      assert(data_transfer_cnt === 0.U)
217    }.otherwise{
218      schedule_csr_op_resp_data := false.B
219      schedule_csr_op_resp_finish := true.B
220    }
221  }
222
223  // Translate cache op resp to CSR write, send it back to CSR
224  when(io.csr.update.w.fire() && schedule_csr_op_resp_data && data_transfer_finished){
225    schedule_csr_op_resp_data := false.B
226    schedule_csr_op_resp_finish := true.B
227  }
228  when(io.csr.update.w.fire() && schedule_csr_op_resp_finish){
229    schedule_csr_op_resp_finish := false.B
230    wait_csr_op_req := true.B
231  }
232
233  io.csr.update.w.valid := schedule_csr_op_resp_data || schedule_csr_op_resp_finish
234  io.csr.update.w.bits := DontCare
235
236  val isReadTagECC = WireInit(CacheInstrucion.isReadTagECC(translated_cache_req.opCode))
237  val isReadDataECC = WireInit(CacheInstrucion.isReadDataECC(translated_cache_req.opCode))
238  val isReadTag = WireInit(CacheInstrucion.isReadTag(translated_cache_req.opCode))
239  val isReadData = WireInit(CacheInstrucion.isReadData(translated_cache_req.opCode))
240
241  when(schedule_csr_op_resp_data){
242    io.csr.update.w.bits.addr := Mux1H(List(
243      isReadTagECC -> (CacheInstrucion.CacheInsRegisterList("CACHE_TAG_ECC")("offset").toInt + Scachebase).U,
244      isReadDataECC -> (CacheInstrucion.CacheInsRegisterList("CACHE_DATA_ECC")("offset").toInt + Scachebase).U,
245      isReadTag -> ((CacheInstrucion.CacheInsRegisterList("CACHE_TAG_LOW")("offset").toInt + Scachebase).U + data_transfer_cnt),
246      isReadData -> ((CacheInstrucion.CacheInsRegisterList("CACHE_DATA_0")("offset").toInt + Scachebase).U + data_transfer_cnt),
247    ))
248    io.csr.update.w.bits.data := Mux1H(List(
249      isReadTagECC -> raw_cache_resp.read_tag_ecc,
250      isReadDataECC -> raw_cache_resp.read_data_ecc,
251      isReadTag -> raw_cache_resp.read_tag_low,
252      isReadData -> raw_cache_resp.read_data_vec(data_transfer_cnt),
253    ))
254    data_transfer_finished := Mux(isReadData,
255      data_transfer_cnt === (maxDataRowSupport-1).U,
256      true.B
257    )
258    data_transfer_cnt := data_transfer_cnt + 1.U
259  }
260
261  when(schedule_csr_op_resp_finish){
262    io.csr.update.w.bits.addr := (CacheInstrucion.CacheInsRegisterList("OP_FINISH")("offset").toInt + Scachebase).U
263    io.csr.update.w.bits.data := CacheInstrucion.COP_RESULT_CODE_OK
264    data_transfer_cnt := 0.U
265  }
266
267  val error = DelayN(io.error, 1)
268  when(error.report_to_beu) {
269    io.csr.update.w.bits.addr := (CacheInstrucion.CacheInsRegisterList("CACHE_ERROR")("offset").toInt + Scachebase).U
270    io.csr.update.w.bits.data := error.asUInt
271    io.csr.update.w.valid := true.B
272  }
273}
274
275class CSRCacheErrorDecoder(implicit p: Parameters) extends CacheCtrlModule {
276  val io = IO(new Bundle{
277    val encoded_cache_error = Input(UInt())
278  })
279  val encoded_cache_error = io.encoded_cache_error
280  def print_cache_error_flag(flag: Bool, desc: String) = {
281    when(flag){
282      printf("  " + desc + "\n")
283    }
284  }
285  val decoded_cache_error = WireInit(encoded_cache_error.asTypeOf(new L1CacheErrorInfo))
286  when(decoded_cache_error.valid && !RegNext(decoded_cache_error.valid)){
287    printf("CACHE_ERROR CSR reported an error:\n")
288    printf("  paddr 0x%x\n", decoded_cache_error.paddr)
289    print_cache_error_flag(decoded_cache_error.report_to_beu, "report to bus error unit")
290    print_cache_error_flag(decoded_cache_error.source.tag, "tag")
291    print_cache_error_flag(decoded_cache_error.source.data, "data")
292    print_cache_error_flag(decoded_cache_error.source.l2, "l2")
293    print_cache_error_flag(decoded_cache_error.opType.fetch, "fetch")
294    print_cache_error_flag(decoded_cache_error.opType.load, "load")
295    print_cache_error_flag(decoded_cache_error.opType.store, "store")
296    print_cache_error_flag(decoded_cache_error.opType.probe, "probe")
297    print_cache_error_flag(decoded_cache_error.opType.release, "release")
298    print_cache_error_flag(decoded_cache_error.opType.atom, "atom")
299    printf("It should not happen in normal execution flow\n")
300  }
301}