1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// See LICENSE.Berkeley for license details. 18 19package xiangshan.cache 20 21import chisel3._ 22import chisel3.util._ 23import xiangshan.XSBundle 24 25trait MemoryOpConstants { 26 val NUM_XA_OPS = 9 27 val M_SZ = 5 28 def M_X = BitPat("b?????") 29 def M_XRD = "b00000".U // int load 30 def M_XWR = "b00001".U // int store 31 def M_PFR = "b00010".U // prefetch with intent to read 32 def M_PFW = "b00011".U // prefetch with intent to write 33 def M_XA_SWAP = "b00100".U 34 def M_FLUSH_ALL = "b00101".U // flush all lines 35 def M_XLR = "b00110".U 36 def M_XSC = "b00111".U 37 def M_XA_ADD = "b01000".U 38 def M_XA_XOR = "b01001".U 39 def M_XA_OR = "b01010".U 40 def M_XA_AND = "b01011".U 41 def M_XA_MIN = "b01100".U 42 def M_XA_MAX = "b01101".U 43 def M_XA_MINU = "b01110".U 44 def M_XA_MAXU = "b01111".U 45 def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions 46 def M_PWR = "b10001".U // partial (masked.U store 47 def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions 48 def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions 49 def M_SFENCE = "b10100".U // flush TLB 50 def M_WOK = "b10111".U // check write permissions but don't perform a write 51 52 def isAMOLogical(cmd: UInt) = cmd === M_XA_SWAP || cmd === M_XA_XOR || cmd === M_XA_OR || cmd === M_XA_AND 53 def isAMOArithmetic(cmd: UInt) = cmd === M_XA_ADD || cmd === M_XA_MIN || cmd === M_XA_MAX || cmd === M_XA_MINU || cmd === M_XA_MAXU 54 def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) 55 def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW 56 def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd) 57 def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) 58 def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR 59} 60 61object MemoryOpConstants extends MemoryOpConstants { 62 def getMemoryOpName(cmd: UInt): String = { 63 val opNames = Map( 64 M_XRD -> "M_XRD", 65 M_XWR -> "M_XWR", 66 M_PFR -> "M_PFR", 67 M_PFW -> "M_PFW", 68 M_XA_SWAP -> "M_XA_SWAP", 69 M_FLUSH_ALL -> "M_FLUSH_ALL", 70 M_XLR -> "M_XLR", 71 M_XSC -> "M_XSC", 72 M_XA_ADD -> "M_XA_ADD", 73 M_XA_XOR -> "M_XA_XOR", 74 M_XA_OR -> "M_XA_OR", 75 M_XA_AND -> "M_XA_AND", 76 M_XA_MIN -> "M_XA_MIN", 77 M_XA_MAX -> "M_XA_MAX", 78 M_XA_MINU -> "M_XA_MINU", 79 M_XA_MAXU -> "M_XA_MAXU", 80 M_FLUSH -> "M_FLUSH", 81 M_PWR -> "M_PWR", 82 M_PRODUCE -> "M_PRODUCE", 83 M_CLEAN -> "M_CLEAN", 84 M_SFENCE -> "M_SFENCE", 85 M_WOK -> "M_WOK" 86 ) 87 val opLitNames = opNames map {case (k, v) => (k.litValue.longValue, v)} 88 return opLitNames(cmd.litValue.longValue) 89 } 90} 91