1a8db15d8Sfdypackage xiangshan.backend.rob 2a8db15d8Sfdy 383ba63b3SXuan Huimport org.chipsalliance.cde.config.Parameters 4a8db15d8Sfdyimport chisel3._ 5a8db15d8Sfdyimport chisel3.util._ 6a8db15d8Sfdyimport xiangshan._ 7a8db15d8Sfdyimport utils._ 8a8db15d8Sfdyimport utility._ 9a8db15d8Sfdyimport xiangshan.backend.Bundles.DynInst 10e43bb916SXuan Huimport xiangshan.backend.{RabToVecExcpMod, RegWriteFromRab} 11a8db15d8Sfdyimport xiangshan.backend.decode.VectorConstants 1244369838SXuan Huimport xiangshan.backend.rename.SnapshotGenerator 13e43bb916SXuan Huimport chisel3.experimental.BundleLiterals._ 1444369838SXuan Hu 1544369838SXuan Huclass RenameBufferPtr(size: Int) extends CircularQueuePtr[RenameBufferPtr](size) { 1644369838SXuan Hu def this()(implicit p: Parameters) = this(p(XSCoreParamsKey).RabSize) 1744369838SXuan Hu} 1844369838SXuan Hu 1944369838SXuan Huobject RenameBufferPtr { 2044369838SXuan Hu def apply(flag: Boolean = false, v: Int = 0)(implicit p: Parameters): RenameBufferPtr = { 2144369838SXuan Hu val ptr = Wire(new RenameBufferPtr(p(XSCoreParamsKey).RabSize)) 2244369838SXuan Hu ptr.flag := flag.B 2344369838SXuan Hu ptr.value := v.U 2444369838SXuan Hu ptr 2544369838SXuan Hu } 2644369838SXuan Hu} 27a8db15d8Sfdy 286b102a39SHaojin Tangclass RenameBufferEntry(implicit p: Parameters) extends XSBundle { 296b102a39SHaojin Tang val info = new RabCommitInfo 306b102a39SHaojin Tang val robIdx = OptionWrapper(!env.FPGAPlatform, new RobPtr) 31870f462dSXuan Hu} 32870f462dSXuan Hu 33a8db15d8Sfdyclass RenameBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 34a8db15d8Sfdy val io = IO(new Bundle { 3544369838SXuan Hu val redirect = Input(ValidIO(new Bundle { 3644369838SXuan Hu })) 37a8db15d8Sfdy 38a8db15d8Sfdy val req = Vec(RenameWidth, Flipped(ValidIO(new DynInst))) 3965f65924SXuan Hu val fromRob = new Bundle { 40a8db15d8Sfdy val walkSize = Input(UInt(log2Up(size).W)) 4165f65924SXuan Hu val walkEnd = Input(Bool()) 42a8db15d8Sfdy val commitSize = Input(UInt(log2Up(size).W)) 43e43bb916SXuan Hu val vecLoadExcp = Input(ValidIO(new Bundle{ 44e43bb916SXuan Hu val isStrided = Bool() 45e43bb916SXuan Hu val isVlm = Bool() 46e43bb916SXuan Hu })) 4765f65924SXuan Hu } 4865f65924SXuan Hu 4944369838SXuan Hu val snpt = Input(new SnapshotPort) 5044369838SXuan Hu 5144369838SXuan Hu val canEnq = Output(Bool()) 525540bdc7Sxiaofeibao val canEnqForDispatch = Output(Bool()) 5344369838SXuan Hu val enqPtrVec = Output(Vec(RenameWidth, new RenameBufferPtr)) 5481535d7bSsinsanction 556b102a39SHaojin Tang val commits = Output(new RabCommitIO) 5663d67ef3STang Haojin val diffCommits = if (backendParams.basicDebugEn) Some(Output(new DiffCommitIO)) else None 5765f65924SXuan Hu 5865f65924SXuan Hu val status = Output(new Bundle { 5965f65924SXuan Hu val walkEnd = Bool() 60ddb49062SXuan Hu val commitEnd = Bool() 6165f65924SXuan Hu }) 62e43bb916SXuan Hu val toVecExcpMod = Output(new RabToVecExcpMod) 63a8db15d8Sfdy }) 64a8db15d8Sfdy 6588034bf0SXuan Hu // alias 6688034bf0SXuan Hu private val snptSelect = io.snpt.snptSelect 6788034bf0SXuan Hu 68a8db15d8Sfdy // pointer 6944369838SXuan Hu private val enqPtrVec = RegInit(VecInit.tabulate(RenameWidth)(idx => RenameBufferPtr(flag = false, idx))) 7044369838SXuan Hu private val enqPtr = enqPtrVec.head 7144369838SXuan Hu private val enqPtrOH = RegInit(1.U(size.W)) 7244369838SXuan Hu private val enqPtrOHShift = CircularShift(enqPtrOH) 7344369838SXuan Hu // may shift [0, RenameWidth] steps 7444369838SXuan Hu private val enqPtrOHVec = VecInit.tabulate(RenameWidth + 1)(enqPtrOHShift.left) 7544369838SXuan Hu private val enqPtrVecNext = Wire(enqPtrVec.cloneType) 7644369838SXuan Hu 77780712aaSxiaofeibao-xjtu private val deqPtrVec = RegInit(VecInit.tabulate(RabCommitWidth)(idx => RenameBufferPtr(flag = false, idx))) 7844369838SXuan Hu private val deqPtr = deqPtrVec.head 7944369838SXuan Hu private val deqPtrOH = RegInit(1.U(size.W)) 8044369838SXuan Hu private val deqPtrOHShift = CircularShift(deqPtrOH) 81780712aaSxiaofeibao-xjtu private val deqPtrOHVec = VecInit.tabulate(RabCommitWidth + 1)(deqPtrOHShift.left) 8244369838SXuan Hu private val deqPtrVecNext = Wire(deqPtrVec.cloneType) 8344369838SXuan Hu XSError(deqPtr.toOH =/= deqPtrOH, p"wrong one-hot reg between $deqPtr and $deqPtrOH") 8444369838SXuan Hu 8544369838SXuan Hu private val walkPtr = Reg(new RenameBufferPtr) 8644369838SXuan Hu private val walkPtrOH = walkPtr.toOH 87780712aaSxiaofeibao-xjtu private val walkPtrOHVec = VecInit.tabulate(RabCommitWidth + 1)(CircularShift(walkPtrOH).left) 8844369838SXuan Hu private val walkPtrNext = Wire(new RenameBufferPtr) 8944369838SXuan Hu 909b9e991bSHaojin Tang private val walkPtrSnapshots = SnapshotGenerator(enqPtr, io.snpt.snptEnq, io.snpt.snptDeq, io.redirect.valid, io.snpt.flushVec) 9188034bf0SXuan Hu 92a8db15d8Sfdy val vcfgPtrOH = RegInit(1.U(size.W)) 93a8db15d8Sfdy val vcfgPtrOHShift = CircularShift(vcfgPtrOH) 94a8db15d8Sfdy // may shift [0, 2) steps 95a8db15d8Sfdy val vcfgPtrOHVec = VecInit.tabulate(2)(vcfgPtrOHShift.left) 96a8db15d8Sfdy 97ffc4f3c2SHaojin Tang val diffPtr = RegInit(0.U.asTypeOf(new RenameBufferPtr)) 98ffc4f3c2SHaojin Tang val diffPtrNext = Wire(new RenameBufferPtr) 9944369838SXuan Hu // Regs 100d3a32fa0Sxiaofeibao val renameBuffer = Reg(Vec(size, new RenameBufferEntry)) 101ffc4f3c2SHaojin Tang val renameBufferEntries = VecInit((0 until size) map (i => renameBuffer(i))) 10244369838SXuan Hu 103e43bb916SXuan Hu val vecLoadExcp = Reg(io.fromRob.vecLoadExcp.cloneType) 104e43bb916SXuan Hu 105e43bb916SXuan Hu private val maxLMUL = 8 106e43bb916SXuan Hu private val vdIdxWidth = log2Up(maxLMUL + 1) 107e43bb916SXuan Hu val currentVdIdx = Reg(UInt(vdIdxWidth.W)) // store 0~8 108e43bb916SXuan Hu 10965f65924SXuan Hu val s_idle :: s_special_walk :: s_walk :: Nil = Enum(3) 11044369838SXuan Hu val state = RegInit(s_idle) 11165f65924SXuan Hu val stateNext = WireInit(state) // otherwise keep state value 11244369838SXuan Hu 11365f65924SXuan Hu private val robWalkEndReg = RegInit(false.B) 11465f65924SXuan Hu private val robWalkEnd = io.fromRob.walkEnd || robWalkEndReg 11544369838SXuan Hu 11644369838SXuan Hu when(io.redirect.valid) { 11765f65924SXuan Hu robWalkEndReg := false.B 11865f65924SXuan Hu }.elsewhen(io.fromRob.walkEnd) { 11965f65924SXuan Hu robWalkEndReg := true.B 12044369838SXuan Hu } 121a8db15d8Sfdy 122a8db15d8Sfdy val realNeedAlloc = io.req.map(req => req.valid && req.bits.needWriteRf) 123a8db15d8Sfdy val enqCount = PopCount(realNeedAlloc) 1247a5f6e11Slewislzh val commitNum = Wire(UInt(log2Up(RabCommitWidth).W)) 1257a5f6e11Slewislzh val walkNum = Wire(UInt(log2Up(RabCommitWidth).W)) 1267a5f6e11Slewislzh commitNum := Mux(io.commits.commitValid(0), PriorityMux((0 until RabCommitWidth).map( 1277a5f6e11Slewislzh i => io.commits.commitValid(RabCommitWidth - 1 - i) -> (RabCommitWidth - i).U 128618b89e6Slewislzh )), 0.U) 1297a5f6e11Slewislzh walkNum := Mux(io.commits.walkValid(0), PriorityMux((0 until RabCommitWidth).map( 1307a5f6e11Slewislzh i => io.commits.walkValid(RabCommitWidth - 1 - i) -> (RabCommitWidth-i).U 131618b89e6Slewislzh )), 0.U) 132618b89e6Slewislzh val commitCount = Mux(io.commits.isCommit && !io.commits.isWalk, commitNum, 0.U) 133618b89e6Slewislzh val walkCount = Mux(io.commits.isWalk && !io.commits.isCommit, walkNum, 0.U) 134618b89e6Slewislzh val specialWalkCount = Mux(io.commits.isCommit && io.commits.isWalk, walkNum, 0.U) 135a8db15d8Sfdy 136a8db15d8Sfdy // number of pair(ldest, pdest) ready to commit to arch_rat 137a8db15d8Sfdy val commitSize = RegInit(0.U(log2Up(size).W)) 138a8db15d8Sfdy val walkSize = RegInit(0.U(log2Up(size).W)) 13965f65924SXuan Hu val specialWalkSize = RegInit(0.U(log2Up(size).W)) 14044369838SXuan Hu 14165f65924SXuan Hu val newCommitSize = io.fromRob.commitSize 14265f65924SXuan Hu val newWalkSize = io.fromRob.walkSize 143a8db15d8Sfdy 14465f65924SXuan Hu val commitSizeNxt = commitSize + newCommitSize - commitCount 14565f65924SXuan Hu val walkSizeNxt = walkSize + newWalkSize - walkCount 14665f65924SXuan Hu 14765f65924SXuan Hu val newSpecialWalkSize = Mux(io.redirect.valid && !io.snpt.useSnpt, commitSizeNxt, 0.U) 14865f65924SXuan Hu val specialWalkSizeNext = specialWalkSize + newSpecialWalkSize - specialWalkCount 14965f65924SXuan Hu 15065f65924SXuan Hu commitSize := Mux(io.redirect.valid && !io.snpt.useSnpt, 0.U, commitSizeNxt) 15165f65924SXuan Hu specialWalkSize := specialWalkSizeNext 1527d086385SXuan Hu walkSize := Mux(io.redirect.valid, 0.U, walkSizeNxt) 153a8db15d8Sfdy 15465f65924SXuan Hu walkPtrNext := MuxCase(walkPtr, Seq( 15588034bf0SXuan Hu (state === s_idle && stateNext === s_walk) -> walkPtrSnapshots(snptSelect), 15665f65924SXuan Hu (state === s_special_walk && stateNext === s_walk) -> deqPtrVecNext.head, 157c4b56310SHaojin Tang (state === s_walk && io.snpt.useSnpt && io.redirect.valid) -> walkPtrSnapshots(snptSelect), 15865f65924SXuan Hu (state === s_walk) -> (walkPtr + walkCount), 15965f65924SXuan Hu )) 16065f65924SXuan Hu 16165f65924SXuan Hu walkPtr := walkPtrNext 16265f65924SXuan Hu 163f1ba628bSHaojin Tang val walkCandidates = VecInit(walkPtrOHVec.map(sel => Mux1H(sel, renameBufferEntries))) 164f1ba628bSHaojin Tang val commitCandidates = VecInit(deqPtrOHVec.map(sel => Mux1H(sel, renameBufferEntries))) 165f1ba628bSHaojin Tang val vcfgCandidates = VecInit(vcfgPtrOHVec.map(sel => Mux1H(sel, renameBufferEntries))) 166a8db15d8Sfdy 167a8db15d8Sfdy // update diff pointer 168ea2894c8SXuan Hu diffPtrNext := diffPtr + newCommitSize 169ffc4f3c2SHaojin Tang diffPtr := diffPtrNext 17044369838SXuan Hu 171a8db15d8Sfdy // update vcfg pointer 172ffc4f3c2SHaojin Tang // TODO: do not use diffPtrNext here 173ffc4f3c2SHaojin Tang vcfgPtrOH := diffPtrNext.toOH 174a8db15d8Sfdy 17544369838SXuan Hu // update enq pointer 17644369838SXuan Hu val enqPtrNext = Mux( 17765f65924SXuan Hu state === s_walk && stateNext === s_idle, 17844369838SXuan Hu walkPtrNext, 17944369838SXuan Hu enqPtr + enqCount 18044369838SXuan Hu ) 18144369838SXuan Hu val enqPtrOHNext = Mux( 18265f65924SXuan Hu state === s_walk && stateNext === s_idle, 18344369838SXuan Hu walkPtrNext.toOH, 18444369838SXuan Hu enqPtrOHVec(enqCount) 18544369838SXuan Hu ) 18644369838SXuan Hu enqPtr := enqPtrNext 18744369838SXuan Hu enqPtrOH := enqPtrOHNext 18844369838SXuan Hu enqPtrVecNext.zipWithIndex.map{ case(ptr, i) => ptr := enqPtrNext + i.U } 18944369838SXuan Hu enqPtrVec := enqPtrVecNext 19044369838SXuan Hu 19165f65924SXuan Hu val deqPtrSteps = Mux1H(Seq( 19265f65924SXuan Hu (state === s_idle) -> commitCount, 19365f65924SXuan Hu (state === s_special_walk) -> specialWalkCount, 19465f65924SXuan Hu )) 19565f65924SXuan Hu 19644369838SXuan Hu // update deq pointer 19765f65924SXuan Hu val deqPtrNext = deqPtr + deqPtrSteps 19865f65924SXuan Hu val deqPtrOHNext = deqPtrOHVec(deqPtrSteps) 19944369838SXuan Hu deqPtr := deqPtrNext 20044369838SXuan Hu deqPtrOH := deqPtrOHNext 20144369838SXuan Hu deqPtrVecNext.zipWithIndex.map{ case(ptr, i) => ptr := deqPtrNext + i.U } 20244369838SXuan Hu deqPtrVec := deqPtrVecNext 20344369838SXuan Hu 20444369838SXuan Hu val allocatePtrVec = VecInit((0 until RenameWidth).map(i => enqPtrVec(PopCount(realNeedAlloc.take(i))).value)) 205a8db15d8Sfdy allocatePtrVec.zip(io.req).zip(realNeedAlloc).map{ case((allocatePtr, req), realNeedAlloc) => 206a8db15d8Sfdy when(realNeedAlloc){ 2076b102a39SHaojin Tang renameBuffer(allocatePtr).info := req.bits 2086b102a39SHaojin Tang renameBuffer(allocatePtr).robIdx.foreach(_ := req.bits.robIdx) 209a8db15d8Sfdy } 210a8db15d8Sfdy } 211a8db15d8Sfdy 21265f65924SXuan Hu io.commits.isCommit := state === s_idle || state === s_special_walk 21365f65924SXuan Hu io.commits.isWalk := state === s_walk || state === s_special_walk 214a8db15d8Sfdy 215780712aaSxiaofeibao-xjtu for(i <- 0 until RabCommitWidth) { 21665f65924SXuan Hu io.commits.commitValid(i) := state === s_idle && i.U < commitSize || state === s_special_walk && i.U < specialWalkSize 21765f65924SXuan Hu io.commits.walkValid(i) := state === s_walk && i.U < walkSize || state === s_special_walk && i.U < specialWalkSize 21865f65924SXuan Hu // special walk use commitPtr 2196b102a39SHaojin Tang io.commits.info(i) := Mux(state === s_idle || state === s_special_walk, commitCandidates(i).info, walkCandidates(i).info) 2206b102a39SHaojin Tang io.commits.robIdx.foreach(_(i) := Mux(state === s_idle || state === s_special_walk, commitCandidates(i).robIdx.get, walkCandidates(i).robIdx.get)) 221a8db15d8Sfdy } 222a8db15d8Sfdy 22365f65924SXuan Hu private val walkEndNext = walkSizeNxt === 0.U 224ddb49062SXuan Hu private val commitEndNext = commitSizeNxt === 0.U 22565d838c0Sxiaofeibao-xjtu private val specialWalkEndNext = specialWalkSize <= RabCommitWidth.U 22665d838c0Sxiaofeibao-xjtu // when robWalkEndReg is 1, walkSize donot increase and decrease RabCommitWidth per Cycle 22765d838c0Sxiaofeibao-xjtu private val walkEndNextCycle = (robWalkEndReg || io.fromRob.walkEnd && io.fromRob.walkSize === 0.U) && (walkSize <= RabCommitWidth.U) 22865f65924SXuan Hu // change state 22965f65924SXuan Hu state := stateNext 23065f65924SXuan Hu when(io.redirect.valid) { 23165f65924SXuan Hu when(io.snpt.useSnpt) { 23265f65924SXuan Hu stateNext := s_walk 23365f65924SXuan Hu }.otherwise { 23465f65924SXuan Hu stateNext := s_special_walk 235e43bb916SXuan Hu vecLoadExcp := io.fromRob.vecLoadExcp 236e43bb916SXuan Hu when(io.fromRob.vecLoadExcp.valid) { 237e43bb916SXuan Hu currentVdIdx := 0.U 238e43bb916SXuan Hu } 23965f65924SXuan Hu } 24065f65924SXuan Hu }.otherwise { 24165f65924SXuan Hu // change stateNext 24265f65924SXuan Hu switch(state) { 24365f65924SXuan Hu // this transaction is not used actually, just list all states 24465f65924SXuan Hu is(s_idle) { 24565f65924SXuan Hu stateNext := s_idle 24665f65924SXuan Hu } 24765f65924SXuan Hu is(s_special_walk) { 248e43bb916SXuan Hu currentVdIdx := currentVdIdx + specialWalkCount 24965f65924SXuan Hu when(specialWalkEndNext) { 25065f65924SXuan Hu stateNext := s_walk 251e43bb916SXuan Hu vecLoadExcp.valid := false.B 25265f65924SXuan Hu } 25365f65924SXuan Hu } 25465f65924SXuan Hu is(s_walk) { 25565d838c0Sxiaofeibao-xjtu when(walkEndNextCycle) { 25665f65924SXuan Hu stateNext := s_idle 25765f65924SXuan Hu } 25865f65924SXuan Hu } 25965f65924SXuan Hu } 26065f65924SXuan Hu } 261a8db15d8Sfdy 26244369838SXuan Hu val numValidEntries = distanceBetween(enqPtr, deqPtr) 2635f8b6c9eSsinceforYy val allowEnqueue = GatedValidRegNext(numValidEntries + enqCount <= (size - RenameWidth).U, true.B) 2645540bdc7Sxiaofeibao val allowEnqueueForDispatch = GatedValidRegNext(numValidEntries + enqCount <= (size - 2*RenameWidth).U, true.B) 265e986c5deSXuan Hu 26682640bc3SHaojin Tang io.canEnq := allowEnqueue && state === s_idle 2675540bdc7Sxiaofeibao io.canEnqForDispatch := allowEnqueueForDispatch && state === s_idle 26844369838SXuan Hu io.enqPtrVec := enqPtrVec 269a8db15d8Sfdy 27065f65924SXuan Hu io.status.walkEnd := walkEndNext 271ddb49062SXuan Hu io.status.commitEnd := commitEndNext 27265f65924SXuan Hu 273e43bb916SXuan Hu for (i <- 0 until RabCommitWidth) { 274*ea7e6d59Sxiaofeibao val valid = (state === s_special_walk) && vecLoadExcp.valid && io.commits.commitValid(i) 275*ea7e6d59Sxiaofeibao io.toVecExcpMod.logicPhyRegMap(i).valid := RegNext(valid) 276e43bb916SXuan Hu io.toVecExcpMod.logicPhyRegMap(i).bits match { 277e43bb916SXuan Hu case x => 278*ea7e6d59Sxiaofeibao x.lreg := RegEnable(io.commits.info(i).ldest, valid) 279*ea7e6d59Sxiaofeibao x.preg := RegEnable(io.commits.info(i).pdest, valid) 280e43bb916SXuan Hu } 281e43bb916SXuan Hu } 282e43bb916SXuan Hu 283a8db15d8Sfdy // for difftest 284cda1c534Sxiaofeibao-xjtu io.diffCommits.foreach(_ := 0.U.asTypeOf(new DiffCommitIO)) 2858ab9d9d0SXuan Hu io.diffCommits.foreach(_.isCommit := true.B) 286780712aaSxiaofeibao-xjtu for(i <- 0 until RabCommitWidth * MaxUopSize) { 2878ab9d9d0SXuan Hu io.diffCommits.foreach(_.commitValid(i) := i.U < newCommitSize) 2886b102a39SHaojin Tang io.diffCommits.foreach(_.info(i) := renameBufferEntries((diffPtr + i.U).value).info) 289a8db15d8Sfdy } 290a8db15d8Sfdy 29144369838SXuan Hu XSError(isBefore(enqPtr, deqPtr) && !isFull(enqPtr, deqPtr), "\ndeqPtr is older than enqPtr!\n") 29289cc69c1STang Haojin 293e986c5deSXuan Hu QueuePerf(RabSize, numValidEntries, numValidEntries === size.U) 294e986c5deSXuan Hu 295780712aaSxiaofeibao-xjtu if (backendParams.debugEn) { 2967d086385SXuan Hu dontTouch(deqPtrVec) 297780712aaSxiaofeibao-xjtu dontTouch(walkPtrNext) 29865d838c0Sxiaofeibao-xjtu dontTouch(walkSizeNxt) 29965d838c0Sxiaofeibao-xjtu dontTouch(walkEndNext) 30065d838c0Sxiaofeibao-xjtu dontTouch(walkEndNextCycle) 301780712aaSxiaofeibao-xjtu } 3027d086385SXuan Hu 303e986c5deSXuan Hu XSPerfAccumulate("s_idle_to_idle", state === s_idle && stateNext === s_idle) 304e986c5deSXuan Hu XSPerfAccumulate("s_idle_to_swlk", state === s_idle && stateNext === s_special_walk) 305e986c5deSXuan Hu XSPerfAccumulate("s_idle_to_walk", state === s_idle && stateNext === s_walk) 306e986c5deSXuan Hu XSPerfAccumulate("s_swlk_to_idle", state === s_special_walk && stateNext === s_idle) 307e986c5deSXuan Hu XSPerfAccumulate("s_swlk_to_swlk", state === s_special_walk && stateNext === s_special_walk) 308e986c5deSXuan Hu XSPerfAccumulate("s_swlk_to_walk", state === s_special_walk && stateNext === s_walk) 309e986c5deSXuan Hu XSPerfAccumulate("s_walk_to_idle", state === s_walk && stateNext === s_idle) 310e986c5deSXuan Hu XSPerfAccumulate("s_walk_to_swlk", state === s_walk && stateNext === s_special_walk) 311e986c5deSXuan Hu XSPerfAccumulate("s_walk_to_walk", state === s_walk && stateNext === s_walk) 312e986c5deSXuan Hu 313e986c5deSXuan Hu XSPerfAccumulate("disallow_enq_cycle", !allowEnqueue) 314e986c5deSXuan Hu XSPerfAccumulate("disallow_enq_full_cycle", numValidEntries + enqCount > (size - RenameWidth).U) 315e986c5deSXuan Hu XSPerfAccumulate("disallow_enq_not_idle_cycle", state =/= s_idle) 316a8db15d8Sfdy} 317