1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.HasCircularQueuePtrHelper 23import utility.ParallelPriorityMux 24import utility.GatedValidRegNext 25import utils.XSError 26import xiangshan._ 27 28abstract class RegType 29case object Reg_I extends RegType 30case object Reg_F extends RegType 31case object Reg_V extends RegType 32 33class RatReadPort(implicit p: Parameters) extends XSBundle { 34 val hold = Input(Bool()) 35 val addr = Input(UInt(6.W)) 36 val data = Output(UInt(PhyRegIdxWidth.W)) 37} 38 39class RatWritePort(implicit p: Parameters) extends XSBundle { 40 val wen = Bool() 41 val addr = UInt(6.W) 42 val data = UInt(PhyRegIdxWidth.W) 43} 44 45class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 46 47 // params alias 48 private val numVecRegSrc = backendParams.numVecRegSrc 49 private val numVecRatPorts = numVecRegSrc 50 51 val readPortsNum = reg_t match { 52 case Reg_I => 2 53 case Reg_F => 3 54 case Reg_V => numVecRatPorts // +1 ldest 55 } 56 val io = IO(new Bundle { 57 val redirect = Input(Bool()) 58 val readPorts = Vec(readPortsNum * RenameWidth, new RatReadPort) 59 val specWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 60 val archWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 61 val old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 62 val need_free = Vec(RabCommitWidth, Output(Bool())) 63 val snpt = Input(new SnapshotPort) 64 val diffWritePorts = if (backendParams.debugEn) Some(Vec(RabCommitWidth * MaxUopSize, Input(new RatWritePort))) else None 65 val debug_rdata = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 66 val debug_vconfig = if (backendParams.debugEn) reg_t match { // vconfig is implemented as int reg[32] 67 case Reg_V => Some(Output(UInt(PhyRegIdxWidth.W))) 68 case _ => None 69 } else None 70 val diff_rdata = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 71 val diff_vconfig = if (backendParams.debugEn) reg_t match { 72 case Reg_V => Some(Output(UInt(PhyRegIdxWidth.W))) 73 case _ => None 74 } else None 75 }) 76 77 // speculative rename table 78 // fp and vec share the same free list, so the first init value of vecRAT is 32 79 val rename_table_init = reg_t match { 80 case Reg_I => VecInit.fill (IntLogicRegs)(0.U(PhyRegIdxWidth.W)) 81 case Reg_F => VecInit.tabulate(FpLogicRegs)(_.U(PhyRegIdxWidth.W)) 82 case Reg_V => VecInit.tabulate(VecLogicRegs)(x => (x + FpLogicRegs).U(PhyRegIdxWidth.W)) 83 } 84 val spec_table = RegInit(rename_table_init) 85 val spec_table_next = WireInit(spec_table) 86 // arch state rename table 87 val arch_table = RegInit(rename_table_init) 88 val arch_table_next = WireDefault(arch_table) 89 // old_pdest 90 val old_pdest = RegInit(VecInit.fill(RabCommitWidth)(0.U(PhyRegIdxWidth.W))) 91 val need_free = RegInit(VecInit.fill(RabCommitWidth)(false.B)) 92 93 // For better timing, we optimize reading and writing to RenameTable as follows: 94 // (1) Writing at T0 will be actually processed at T1. 95 // (2) Reading is synchronous now. 96 // (3) RAddr at T0 will be used to access the table and get data at T0. 97 // (4) WData at T0 is bypassed to RData at T1. 98 val t1_redirect = GatedValidRegNext(io.redirect, false.B) 99 val t1_raddr = io.readPorts.map(p => RegEnable(p.addr, !p.hold)) 100 val t1_rdata_use_t1_raddr = VecInit(t1_raddr.map(spec_table(_))) 101 val t1_wSpec = RegNext(Mux(io.redirect, 0.U.asTypeOf(io.specWritePorts), io.specWritePorts)) 102 103 val t1_snpt = RegNext(io.snpt, 0.U.asTypeOf(io.snpt)) 104 105 val snapshots = SnapshotGenerator(spec_table, t1_snpt.snptEnq, t1_snpt.snptDeq, t1_redirect, t1_snpt.flushVec) 106 107 // WRITE: when instruction commits or walking 108 val t1_wSpec_addr = t1_wSpec.map(w => Mux(w.wen, UIntToOH(w.addr), 0.U)) 109 for ((next, i) <- spec_table_next.zipWithIndex) { 110 val matchVec = t1_wSpec_addr.map(w => w(i)) 111 val wMatch = ParallelPriorityMux(matchVec.reverse, t1_wSpec.map(_.data).reverse) 112 // When there's a flush, we use arch_table to update spec_table. 113 next := Mux( 114 t1_redirect, 115 Mux(t1_snpt.useSnpt, snapshots(t1_snpt.snptSelect)(i), arch_table(i)), 116 Mux(VecInit(matchVec).asUInt.orR, wMatch, spec_table(i)) 117 ) 118 } 119 spec_table := spec_table_next 120 121 // READ: decode-rename stage 122 for ((r, i) <- io.readPorts.zipWithIndex) { 123 val t0_bypass = io.specWritePorts.map(w => w.wen && Mux(r.hold, w.addr === t1_raddr(i), w.addr === r.addr)) 124 val t1_bypass = RegNext(Mux(io.redirect, 0.U.asTypeOf(VecInit(t0_bypass)), VecInit(t0_bypass))) 125 val bypass_data = ParallelPriorityMux(t1_bypass.reverse, t1_wSpec.map(_.data).reverse) 126 r.data := Mux(t1_bypass.asUInt.orR, bypass_data, t1_rdata_use_t1_raddr(i)) 127 } 128 129 for ((w, i) <- io.archWritePorts.zipWithIndex) { 130 when (w.wen) { 131 arch_table_next(w.addr) := w.data 132 } 133 val arch_mask = VecInit.fill(PhyRegIdxWidth)(w.wen).asUInt 134 old_pdest(i) := 135 MuxCase(arch_table(w.addr) & arch_mask, 136 io.archWritePorts.take(i).reverse.map(x => (x.wen && x.addr === w.addr, x.data & arch_mask))) 137 } 138 arch_table := arch_table_next 139 140 for (((old, free), i) <- (old_pdest zip need_free).zipWithIndex) { 141 val hasDuplicate = old_pdest.take(i).map(_ === old) 142 val blockedByDup = if (i == 0) false.B else VecInit(hasDuplicate).asUInt.orR 143 free := VecInit(arch_table.map(_ =/= old)).asUInt.andR && !blockedByDup 144 } 145 146 io.old_pdest := old_pdest 147 io.need_free := need_free 148 io.debug_rdata.foreach(_ := arch_table.take(32)) 149 io.debug_vconfig match { 150 case None => 151 case x => x.get := arch_table.last 152 } 153 if (env.EnableDifftest || env.AlwaysBasicDiff) { 154 val difftest_table = RegInit(rename_table_init) 155 val difftest_table_next = WireDefault(difftest_table) 156 157 for (w <- io.diffWritePorts.get) { 158 when(w.wen) { 159 difftest_table_next(w.addr) := w.data 160 } 161 } 162 difftest_table := difftest_table_next 163 164 io.diff_rdata.foreach(_ := difftest_table.take(32)) 165 io.diff_vconfig match { 166 case None => 167 case x => x.get := difftest_table(VCONFIG_IDX) 168 } 169 } 170 else { 171 io.diff_rdata.foreach(_ := 0.U.asTypeOf(io.debug_rdata.get)) 172 io.diff_vconfig match { 173 case None => 174 case x => x.get := 0.U 175 } 176 } 177} 178 179class RenameTableWrapper(implicit p: Parameters) extends XSModule { 180 181 // params alias 182 private val numVecRegSrc = backendParams.numVecRegSrc 183 private val numVecRatPorts = numVecRegSrc 184 185 val io = IO(new Bundle() { 186 val redirect = Input(Bool()) 187 val rabCommits = Input(new RabCommitIO) 188 val diffCommits = if (backendParams.debugEn) Some(Input(new DiffCommitIO)) else None 189 val intReadPorts = Vec(RenameWidth, Vec(2, new RatReadPort)) 190 val intRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 191 val fpReadPorts = Vec(RenameWidth, Vec(3, new RatReadPort)) 192 val fpRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 193 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, new RatReadPort)) 194 val vecRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 195 196 val int_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 197 val fp_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 198 val vec_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 199 val int_need_free = Vec(RabCommitWidth, Output(Bool())) 200 val snpt = Input(new SnapshotPort) 201 202 // for debug printing 203 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 204 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 205 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 206 val debug_vconfig_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 207 208 val diff_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 209 val diff_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 210 val diff_vec_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 211 val diff_vconfig_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 212 }) 213 214 val intRat = Module(new RenameTable(Reg_I)) 215 val fpRat = Module(new RenameTable(Reg_F)) 216 val vecRat = Module(new RenameTable(Reg_V)) 217 218 io.debug_int_rat .foreach(_ := intRat.io.debug_rdata.get) 219 io.diff_int_rat .foreach(_ := intRat.io.diff_rdata.get) 220 intRat.io.readPorts <> io.intReadPorts.flatten 221 intRat.io.redirect := io.redirect 222 intRat.io.snpt := io.snpt 223 io.int_old_pdest := intRat.io.old_pdest 224 io.int_need_free := intRat.io.need_free 225 val intDestValid = io.rabCommits.info.map(_.rfWen) 226 for ((arch, i) <- intRat.io.archWritePorts.zipWithIndex) { 227 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && intDestValid(i) 228 arch.addr := io.rabCommits.info(i).ldest 229 arch.data := io.rabCommits.info(i).pdest 230 XSError(arch.wen && arch.addr === 0.U && arch.data =/= 0.U, "pdest for $0 should be 0\n") 231 } 232 for ((spec, i) <- intRat.io.specWritePorts.zipWithIndex) { 233 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && intDestValid(i) 234 spec.addr := io.rabCommits.info(i).ldest 235 spec.data := io.rabCommits.info(i).pdest 236 XSError(spec.wen && spec.addr === 0.U && spec.data =/= 0.U, "pdest for $0 should be 0\n") 237 } 238 for ((spec, rename) <- intRat.io.specWritePorts.zip(io.intRenamePorts)) { 239 when (rename.wen) { 240 spec.wen := true.B 241 spec.addr := rename.addr 242 spec.data := rename.data 243 } 244 } 245 if (backendParams.debugEn) { 246 for ((diff, i) <- intRat.io.diffWritePorts.get.zipWithIndex) { 247 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).rfWen 248 diff.addr := io.diffCommits.get.info(i).ldest 249 diff.data := io.diffCommits.get.info(i).pdest 250 } 251 } 252 253 // debug read ports for difftest 254 io.debug_fp_rat.foreach(_ := fpRat.io.debug_rdata.get) 255 io.diff_fp_rat .foreach(_ := fpRat.io.diff_rdata.get) 256 fpRat.io.readPorts <> io.fpReadPorts.flatten 257 fpRat.io.redirect := io.redirect 258 fpRat.io.snpt := io.snpt 259 io.fp_old_pdest := fpRat.io.old_pdest 260 261 for ((arch, i) <- fpRat.io.archWritePorts.zipWithIndex) { 262 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).fpWen 263 arch.addr := io.rabCommits.info(i).ldest 264 arch.data := io.rabCommits.info(i).pdest 265 } 266 for ((spec, i) <- fpRat.io.specWritePorts.zipWithIndex) { 267 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).fpWen 268 spec.addr := io.rabCommits.info(i).ldest 269 spec.data := io.rabCommits.info(i).pdest 270 } 271 for ((spec, rename) <- fpRat.io.specWritePorts.zip(io.fpRenamePorts)) { 272 when (rename.wen) { 273 spec.wen := true.B 274 spec.addr := rename.addr 275 spec.data := rename.data 276 } 277 } 278 if (backendParams.debugEn) { 279 for ((diff, i) <- fpRat.io.diffWritePorts.get.zipWithIndex) { 280 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).fpWen 281 diff.addr := io.diffCommits.get.info(i).ldest 282 diff.data := io.diffCommits.get.info(i).pdest 283 } 284 } 285 // debug read ports for difftest 286 io.debug_vec_rat .foreach(_ := vecRat.io.debug_rdata.get) 287 io.debug_vconfig_rat.foreach(_ := vecRat.io.debug_vconfig.get) 288 io.diff_vec_rat .foreach(_ := vecRat.io.diff_rdata.get) 289 io.diff_vconfig_rat .foreach(_ := vecRat.io.diff_vconfig.get) 290 vecRat.io.readPorts <> io.vecReadPorts.flatten 291 vecRat.io.redirect := io.redirect 292 vecRat.io.snpt := io.snpt 293 io.vec_old_pdest := vecRat.io.old_pdest 294 295 //TODO: RM the donTouch 296 if(backendParams.debugEn) { 297 dontTouch(vecRat.io) 298 } 299 for ((arch, i) <- vecRat.io.archWritePorts.zipWithIndex) { 300 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vecWen 301 arch.addr := io.rabCommits.info(i).ldest 302 arch.data := io.rabCommits.info(i).pdest 303 } 304 for ((spec, i) <- vecRat.io.specWritePorts.zipWithIndex) { 305 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vecWen 306 spec.addr := io.rabCommits.info(i).ldest 307 spec.data := io.rabCommits.info(i).pdest 308 } 309 for ((spec, rename) <- vecRat.io.specWritePorts.zip(io.vecRenamePorts)) { 310 when (rename.wen) { 311 spec.wen := true.B 312 spec.addr := rename.addr 313 spec.data := rename.data 314 } 315 } 316 if (backendParams.debugEn) { 317 for ((diff, i) <- vecRat.io.diffWritePorts.get.zipWithIndex) { 318 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vecWen 319 diff.addr := io.diffCommits.get.info(i).ldest 320 diff.data := io.diffCommits.get.info(i).pdest 321 } 322 } 323} 324