1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.HasCircularQueuePtrHelper 23import utility.ParallelPriorityMux 24import utility.GatedValidRegNext 25import utils.XSError 26import xiangshan._ 27 28abstract class RegType 29case object Reg_I extends RegType 30case object Reg_F extends RegType 31case object Reg_V extends RegType 32case object Reg_V0 extends RegType 33case object Reg_Vl extends RegType 34 35class RatReadPort(implicit p: Parameters) extends XSBundle { 36 val hold = Input(Bool()) 37 val addr = Input(UInt(6.W)) 38 val data = Output(UInt(PhyRegIdxWidth.W)) 39} 40 41class RatWritePort(implicit p: Parameters) extends XSBundle { 42 val wen = Bool() 43 val addr = UInt(6.W) 44 val data = UInt(PhyRegIdxWidth.W) 45} 46 47class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 48 49 // params alias 50 private val numVecRegSrc = backendParams.numVecRegSrc 51 private val numVecRatPorts = numVecRegSrc 52 53 val readPortsNum = reg_t match { 54 case Reg_I => 2 55 case Reg_F => 3 56 case Reg_V => numVecRatPorts // +1 ldest 57 case Reg_V0 => 1 58 case Reg_Vl => 1 59 } 60 val rdataNums = reg_t match { 61 case Reg_I => 32 62 case Reg_F => 32 63 case Reg_V => 31 // no v0 64 case Reg_V0 => 1 // v0 65 case Reg_Vl => 1 // vl 66 } 67 val io = IO(new Bundle { 68 val redirect = Input(Bool()) 69 val readPorts = Vec(readPortsNum * RenameWidth, new RatReadPort) 70 val specWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 71 val archWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 72 val old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 73 val need_free = Vec(RabCommitWidth, Output(Bool())) 74 val snpt = Input(new SnapshotPort) 75 val diffWritePorts = if (backendParams.debugEn) Some(Vec(RabCommitWidth * MaxUopSize, Input(new RatWritePort))) else None 76 val debug_rdata = if (backendParams.debugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 77 val diff_rdata = if (backendParams.debugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 78 val debug_v0 = if (backendParams.debugEn) reg_t match { 79 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 80 case _ => None 81 } else None 82 val diff_v0 = if (backendParams.debugEn) reg_t match { 83 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 84 case _ => None 85 } else None 86 val debug_vl = if (backendParams.debugEn) reg_t match { 87 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 88 case _ => None 89 } else None 90 val diff_vl = if (backendParams.debugEn) reg_t match { 91 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 92 case _ => None 93 } else None 94 }) 95 96 // speculative rename table 97 val rename_table_init = reg_t match { 98 case Reg_I => VecInit.fill (IntLogicRegs)(0.U(PhyRegIdxWidth.W)) 99 case Reg_F => VecInit.tabulate(FpLogicRegs)(_.U(PhyRegIdxWidth.W)) 100 case Reg_V => VecInit.tabulate(VecLogicRegs)(_.U(PhyRegIdxWidth.W)) 101// case Reg_V0 => VecInit.tabulate(V0LogicRegs)(_.U(PhyRegIdxWidth.W)) 102// case Reg_Vl => VecInit.tabulate(VlLogicRegs)(_.U(PhyRegIdxWidth.W)) 103 case Reg_V0 => VecInit.tabulate(2)(_.U(PhyRegIdxWidth.W)) 104 case Reg_Vl => VecInit.tabulate(1)(_.U(PhyRegIdxWidth.W)) 105 } 106 val spec_table = RegInit(rename_table_init) 107 val spec_table_next = WireInit(spec_table) 108 // arch state rename table 109 val arch_table = RegInit(rename_table_init) 110 val arch_table_next = WireDefault(arch_table) 111 // old_pdest 112 val old_pdest = RegInit(VecInit.fill(RabCommitWidth)(0.U(PhyRegIdxWidth.W))) 113 val need_free = RegInit(VecInit.fill(RabCommitWidth)(false.B)) 114 115 // For better timing, we optimize reading and writing to RenameTable as follows: 116 // (1) Writing at T0 will be actually processed at T1. 117 // (2) Reading is synchronous now. 118 // (3) RAddr at T0 will be used to access the table and get data at T0. 119 // (4) WData at T0 is bypassed to RData at T1. 120 val t1_redirect = GatedValidRegNext(io.redirect, false.B) 121 val t1_raddr = io.readPorts.map(p => RegEnable(p.addr, !p.hold)) 122 val t1_rdata_use_t1_raddr = VecInit(t1_raddr.map(spec_table(_))) 123 val t1_wSpec = RegNext(Mux(io.redirect, 0.U.asTypeOf(io.specWritePorts), io.specWritePorts)) 124 125 val t1_snpt = RegNext(io.snpt, 0.U.asTypeOf(io.snpt)) 126 127 val snapshots = SnapshotGenerator(spec_table, t1_snpt.snptEnq, t1_snpt.snptDeq, t1_redirect, t1_snpt.flushVec) 128 129 // WRITE: when instruction commits or walking 130 val t1_wSpec_addr = t1_wSpec.map(w => Mux(w.wen, UIntToOH(w.addr), 0.U)) 131 for ((next, i) <- spec_table_next.zipWithIndex) { 132 val matchVec = t1_wSpec_addr.map(w => w(i)) 133 val wMatch = ParallelPriorityMux(matchVec.reverse, t1_wSpec.map(_.data).reverse) 134 // When there's a flush, we use arch_table to update spec_table. 135 next := Mux( 136 t1_redirect, 137 Mux(t1_snpt.useSnpt, snapshots(t1_snpt.snptSelect)(i), arch_table(i)), 138 Mux(VecInit(matchVec).asUInt.orR, wMatch, spec_table(i)) 139 ) 140 } 141 spec_table := spec_table_next 142 143 // READ: decode-rename stage 144 for ((r, i) <- io.readPorts.zipWithIndex) { 145 val t0_bypass = io.specWritePorts.map(w => w.wen && Mux(r.hold, w.addr === t1_raddr(i), w.addr === r.addr)) 146 val t1_bypass = RegNext(Mux(io.redirect, 0.U.asTypeOf(VecInit(t0_bypass)), VecInit(t0_bypass))) 147 val bypass_data = ParallelPriorityMux(t1_bypass.reverse, t1_wSpec.map(_.data).reverse) 148 r.data := Mux(t1_bypass.asUInt.orR, bypass_data, t1_rdata_use_t1_raddr(i)) 149 } 150 151 for ((w, i) <- io.archWritePorts.zipWithIndex) { 152 when (w.wen) { 153 arch_table_next(w.addr) := w.data 154 } 155 val arch_mask = VecInit.fill(PhyRegIdxWidth)(w.wen).asUInt 156 old_pdest(i) := 157 MuxCase(arch_table(w.addr) & arch_mask, 158 io.archWritePorts.take(i).reverse.map(x => (x.wen && x.addr === w.addr, x.data & arch_mask))) 159 } 160 arch_table := arch_table_next 161 162 for (((old, free), i) <- (old_pdest zip need_free).zipWithIndex) { 163 val hasDuplicate = old_pdest.take(i).map(_ === old) 164 val blockedByDup = if (i == 0) false.B else VecInit(hasDuplicate).asUInt.orR 165 free := VecInit(arch_table.map(_ =/= old)).asUInt.andR && !blockedByDup 166 } 167 168 io.old_pdest := old_pdest 169 io.need_free := need_free 170 io.debug_rdata.foreach(_ := arch_table.take(rdataNums)) 171 io.debug_v0.foreach(_ := arch_table(0)) 172 io.debug_vl.foreach(_ := arch_table(0)) 173 if (env.EnableDifftest || env.AlwaysBasicDiff) { 174 val difftest_table = RegInit(rename_table_init) 175 val difftest_table_next = WireDefault(difftest_table) 176 177 for (w <- io.diffWritePorts.get) { 178 when(w.wen) { 179 difftest_table_next(w.addr) := w.data 180 } 181 } 182 difftest_table := difftest_table_next 183 184 io.diff_rdata.foreach(_ := difftest_table.take(rdataNums)) 185 io.diff_v0.foreach(_ := difftest_table(0)) 186 io.diff_vl.foreach(_ := difftest_table(0)) 187 } 188 else { 189 io.diff_rdata.foreach(_ := 0.U.asTypeOf(io.debug_rdata.get)) 190 io.diff_v0.foreach(_ := 0.U) 191 io.diff_vl.foreach(_ := 0.U) 192 } 193} 194 195class RenameTableWrapper(implicit p: Parameters) extends XSModule { 196 197 // params alias 198 private val numVecRegSrc = backendParams.numVecRegSrc 199 private val numVecRatPorts = numVecRegSrc 200 201 val io = IO(new Bundle() { 202 val redirect = Input(Bool()) 203 val rabCommits = Input(new RabCommitIO) 204 val diffCommits = if (backendParams.debugEn) Some(Input(new DiffCommitIO)) else None 205 val intReadPorts = Vec(RenameWidth, Vec(2, new RatReadPort)) 206 val intRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 207 val fpReadPorts = Vec(RenameWidth, Vec(3, new RatReadPort)) 208 val fpRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 209 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, new RatReadPort)) 210 val vecRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 211 val v0ReadPorts = Vec(RenameWidth, new RatReadPort) 212 val v0RenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 213 val vlReadPorts = Vec(RenameWidth, new RatReadPort) 214 val vlRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 215 216 val int_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 217 val fp_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 218 val vec_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 219 val v0_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 220 val vl_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 221 val int_need_free = Vec(RabCommitWidth, Output(Bool())) 222 val snpt = Input(new SnapshotPort) 223 224 // for debug printing 225 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 226 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 227 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 228 val debug_v0_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 229 val debug_vl_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 230 231 val diff_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 232 val diff_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 233 val diff_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 234 val diff_v0_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 235 val diff_vl_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 236 }) 237 238 val intRat = Module(new RenameTable(Reg_I)) 239 val fpRat = Module(new RenameTable(Reg_F)) 240 val vecRat = Module(new RenameTable(Reg_V)) 241 val v0Rat = Module(new RenameTable(Reg_V0)) 242 val vlRat = Module(new RenameTable(Reg_Vl)) 243 244 io.debug_int_rat .foreach(_ := intRat.io.debug_rdata.get) 245 io.diff_int_rat .foreach(_ := intRat.io.diff_rdata.get) 246 intRat.io.readPorts <> io.intReadPorts.flatten 247 intRat.io.redirect := io.redirect 248 intRat.io.snpt := io.snpt 249 io.int_old_pdest := intRat.io.old_pdest 250 io.int_need_free := intRat.io.need_free 251 val intDestValid = io.rabCommits.info.map(_.rfWen) 252 for ((arch, i) <- intRat.io.archWritePorts.zipWithIndex) { 253 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && intDestValid(i) 254 arch.addr := io.rabCommits.info(i).ldest 255 arch.data := io.rabCommits.info(i).pdest 256 XSError(arch.wen && arch.addr === 0.U && arch.data =/= 0.U, "pdest for $0 should be 0\n") 257 } 258 for ((spec, i) <- intRat.io.specWritePorts.zipWithIndex) { 259 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && intDestValid(i) 260 spec.addr := io.rabCommits.info(i).ldest 261 spec.data := io.rabCommits.info(i).pdest 262 XSError(spec.wen && spec.addr === 0.U && spec.data =/= 0.U, "pdest for $0 should be 0\n") 263 } 264 for ((spec, rename) <- intRat.io.specWritePorts.zip(io.intRenamePorts)) { 265 when (rename.wen) { 266 spec.wen := true.B 267 spec.addr := rename.addr 268 spec.data := rename.data 269 } 270 } 271 if (backendParams.debugEn) { 272 for ((diff, i) <- intRat.io.diffWritePorts.get.zipWithIndex) { 273 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).rfWen 274 diff.addr := io.diffCommits.get.info(i).ldest 275 diff.data := io.diffCommits.get.info(i).pdest 276 } 277 } 278 279 // debug read ports for difftest 280 io.debug_fp_rat.foreach(_ := fpRat.io.debug_rdata.get) 281 io.diff_fp_rat .foreach(_ := fpRat.io.diff_rdata.get) 282 fpRat.io.readPorts <> io.fpReadPorts.flatten 283 fpRat.io.redirect := io.redirect 284 fpRat.io.snpt := io.snpt 285 io.fp_old_pdest := fpRat.io.old_pdest 286 287 for ((arch, i) <- fpRat.io.archWritePorts.zipWithIndex) { 288 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).fpWen 289 arch.addr := io.rabCommits.info(i).ldest 290 arch.data := io.rabCommits.info(i).pdest 291 } 292 for ((spec, i) <- fpRat.io.specWritePorts.zipWithIndex) { 293 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).fpWen 294 spec.addr := io.rabCommits.info(i).ldest 295 spec.data := io.rabCommits.info(i).pdest 296 } 297 for ((spec, rename) <- fpRat.io.specWritePorts.zip(io.fpRenamePorts)) { 298 when (rename.wen) { 299 spec.wen := true.B 300 spec.addr := rename.addr 301 spec.data := rename.data 302 } 303 } 304 if (backendParams.debugEn) { 305 for ((diff, i) <- fpRat.io.diffWritePorts.get.zipWithIndex) { 306 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).fpWen 307 diff.addr := io.diffCommits.get.info(i).ldest 308 diff.data := io.diffCommits.get.info(i).pdest 309 } 310 } 311 312 // debug read ports for difftest 313 io.debug_vec_rat .foreach(_ := vecRat.io.debug_rdata.get) 314 io.diff_vec_rat .foreach(_ := vecRat.io.diff_rdata.get) 315 vecRat.io.readPorts <> io.vecReadPorts.flatten 316 vecRat.io.redirect := io.redirect 317 vecRat.io.snpt := io.snpt 318 io.vec_old_pdest := vecRat.io.old_pdest 319 320 //TODO: RM the donTouch 321 if(backendParams.debugEn) { 322 dontTouch(vecRat.io) 323 } 324 for ((arch, i) <- vecRat.io.archWritePorts.zipWithIndex) { 325 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vecWen 326 arch.addr := io.rabCommits.info(i).ldest 327 arch.data := io.rabCommits.info(i).pdest 328 } 329 for ((spec, i) <- vecRat.io.specWritePorts.zipWithIndex) { 330 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vecWen 331 spec.addr := io.rabCommits.info(i).ldest 332 spec.data := io.rabCommits.info(i).pdest 333 } 334 for ((spec, rename) <- vecRat.io.specWritePorts.zip(io.vecRenamePorts)) { 335 when (rename.wen) { 336 spec.wen := true.B 337 spec.addr := rename.addr 338 spec.data := rename.data 339 } 340 } 341 if (backendParams.debugEn) { 342 for ((diff, i) <- vecRat.io.diffWritePorts.get.zipWithIndex) { 343 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vecWen 344 diff.addr := io.diffCommits.get.info(i).ldest 345 diff.data := io.diffCommits.get.info(i).pdest 346 } 347 } 348 349 // debug read ports for difftest 350 io.debug_v0_rat.foreach(_ := v0Rat.io.debug_rdata.get) 351 io.diff_v0_rat.foreach(_ := v0Rat.io.diff_rdata.get) 352 v0Rat.io.readPorts <> io.v0ReadPorts 353 v0Rat.io.redirect := io.redirect 354 v0Rat.io.snpt := io.snpt 355 io.v0_old_pdest := v0Rat.io.old_pdest 356 357 if (backendParams.debugEn) { 358 dontTouch(v0Rat.io) 359 } 360 for ((arch, i) <- v0Rat.io.archWritePorts.zipWithIndex) { 361 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).v0Wen 362 arch.addr := io.rabCommits.info(i).ldest 363 arch.data := io.rabCommits.info(i).pdest 364 } 365 for ((spec, i) <- v0Rat.io.specWritePorts.zipWithIndex) { 366 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).v0Wen 367 spec.addr := io.rabCommits.info(i).ldest 368 spec.data := io.rabCommits.info(i).pdest 369 } 370 for ((spec, rename) <- v0Rat.io.specWritePorts.zip(io.v0RenamePorts)) { 371 when(rename.wen) { 372 spec.wen := true.B 373 spec.addr := rename.addr 374 spec.data := rename.data 375 } 376 } 377 if (backendParams.debugEn) { 378 for ((diff, i) <- v0Rat.io.diffWritePorts.get.zipWithIndex) { 379 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).v0Wen 380 diff.addr := io.diffCommits.get.info(i).ldest 381 diff.data := io.diffCommits.get.info(i).pdest 382 } 383 } 384 385 // debug read ports for difftest 386 io.debug_vl_rat.foreach(_ := vlRat.io.debug_rdata.get) 387 io.diff_vl_rat.foreach(_ := vlRat.io.diff_rdata.get) 388 vlRat.io.readPorts <> io.vlReadPorts 389 vlRat.io.redirect := io.redirect 390 vlRat.io.snpt := io.snpt 391 io.vl_old_pdest := vlRat.io.old_pdest 392 393 if (backendParams.debugEn) { 394 dontTouch(vlRat.io) 395 } 396 for ((arch, i) <- vlRat.io.archWritePorts.zipWithIndex) { 397 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vlWen 398 arch.addr := io.rabCommits.info(i).ldest 399 arch.data := io.rabCommits.info(i).pdest 400 } 401 for ((spec, i) <- vlRat.io.specWritePorts.zipWithIndex) { 402 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vlWen 403 spec.addr := io.rabCommits.info(i).ldest 404 spec.data := io.rabCommits.info(i).pdest 405 } 406 for ((spec, rename) <- vlRat.io.specWritePorts.zip(io.vlRenamePorts)) { 407 when(rename.wen) { 408 spec.wen := true.B 409 spec.addr := rename.addr 410 spec.data := rename.data 411 } 412 } 413 if (backendParams.debugEn) { 414 for ((diff, i) <- vlRat.io.diffWritePorts.get.zipWithIndex) { 415 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vlWen 416 diff.addr := io.diffCommits.get.info(i).ldest 417 diff.data := io.diffCommits.get.info(i).pdest 418 } 419 } 420} 421