1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23 24class RatReadPort(implicit p: Parameters) extends XSBundle { 25 val addr = Input(UInt(5.W)) 26 val rdata = Output(UInt(PhyRegIdxWidth.W)) 27} 28 29class RatWritePort(implicit p: Parameters) extends XSBundle { 30 val wen = Input(Bool()) 31 val addr = Input(UInt(5.W)) 32 val wdata = Input(UInt(PhyRegIdxWidth.W)) 33} 34 35class RenameTable(float: Boolean)(implicit p: Parameters) extends XSModule { 36 val io = IO(new Bundle() { 37 val redirect = Input(Bool()) 38 val flush = Input(Bool()) 39 val walkWen = Input(Bool()) 40 val readPorts = Vec({if(float) 4 else 3} * RenameWidth, new RatReadPort) 41 val specWritePorts = Vec(CommitWidth, new RatWritePort) 42 val archWritePorts = Vec(CommitWidth, new RatWritePort) 43 val debug_rdata = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 44 }) 45 46 // speculative rename table 47 val spec_table = RegInit(VecInit(Seq.tabulate(32)(i => i.U(PhyRegIdxWidth.W)))) 48 49 // arch state rename table 50 val arch_table = RegInit(VecInit(Seq.tabulate(32)(i => i.U(PhyRegIdxWidth.W)))) 51 52 // When redirect happens (mis-prediction), don't update the rename table 53 // However, when mis-prediction and walk happens at the same time, rename table needs to be updated 54 for (w <- io.specWritePorts){ 55 when (w.wen && (!(io.redirect || io.flush) || io.walkWen)) { 56 spec_table(w.addr) := w.wdata 57 } 58 } 59 60 for((r, i) <- io.readPorts.zipWithIndex){ 61 r.rdata := spec_table(r.addr) 62 } 63 64 for(w <- io.archWritePorts){ 65 when(w.wen){ arch_table(w.addr) := w.wdata } 66 } 67 68 when (io.flush) { 69 spec_table := arch_table 70 // spec table needs to be updated when flushPipe 71 for (w <- io.archWritePorts) { 72 when(w.wen){ spec_table(w.addr) := w.wdata } 73 } 74 } 75 76 io.debug_rdata := arch_table 77} 78