1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 26import xiangshan.backend.rob.RobPtr 27import xiangshan.backend.rename.freelist._ 28import xiangshan.mem.mdp._ 29 30class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 31 val io = IO(new Bundle() { 32 val redirect = Flipped(ValidIO(new Redirect)) 33 val robCommits = Input(new RobCommitIO) 34 // from decode 35 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 36 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 37 // ssit read result 38 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 39 // waittable read result 40 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 41 // to rename table 42 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 43 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 44 val vecReadPorts = Vec(RenameWidth, Vec(5, Input(UInt(PhyRegIdxWidth.W)))) 45 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 46 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 47 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 48 // to dispatch1 49 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 50 // debug arch ports 51 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 52 val debug_vconfig_rat = Input(UInt(PhyRegIdxWidth.W)) 53 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 54 }) 55 56 // create free list and rat 57 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 58 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 59 val fpFreeList = Module(new StdFreeList(NRPhyRegs - 64)) 60 61 intRefCounter.io.commit <> io.robCommits 62 intRefCounter.io.redirect := io.redirect.valid 63 intRefCounter.io.debug_int_rat <> io.debug_int_rat 64 intRefCounter.io.debug_vconfig_rat := io.debug_vconfig_rat 65 intFreeList.io.commit <> io.robCommits 66 intFreeList.io.debug_rat <> io.debug_int_rat 67 intFreeList.io_extra.debug_vconfig_rat := io.debug_vconfig_rat 68 fpFreeList.io.commit <> io.robCommits 69 fpFreeList.io.debug_rat <> io.debug_fp_rat 70 71 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 72 // fp and vec share `fpFreeList` 73 def needDestReg[T <: CfCtrl](int: Boolean, x: T): Bool = { 74 if (int) (x.ctrl.rfWen && x.ctrl.ldest =/= 0.U) else x.ctrl.fpVecWen 75 } 76 def needDestReg[T <: CfCtrl](reg_t: RegType, x: T): Bool = reg_t match { 77 case Reg_I => x.ctrl.rfWen && x.ctrl.ldest =/= 0.U 78 case Reg_F => x.ctrl.fpWen 79 case Reg_V => x.ctrl.vecWen 80 } 81 def needDestRegCommit[T <: RobCommitInfo](int: Boolean, x: T): Bool = { 82 if (int) x.rfWen else x.fpVecWen 83 } 84 def needDestRegWalk[T <: RobCommitInfo](int: Boolean, x: T): Bool = { 85 if(int) x.rfWen && x.ldest =/= 0.U else x.fpVecWen 86 } 87 88 // connect [redirect + walk] ports for __float point__ & __integer__ free list 89 Seq(fpFreeList, intFreeList).foreach { case fl => 90 fl.io.redirect := io.redirect.valid 91 fl.io.walk := io.robCommits.isWalk 92 } 93 // only when both fp and int free list and dispatch1 has enough space can we do allocation 94 // when isWalk, freelist can definitely allocate 95 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 96 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 97 98 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 99 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 100 101 102 // speculatively assign the instruction with an robIdx 103 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 104 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 105 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 106 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 107 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 108 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 109 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 110 robIdxHead := robIdxHeadNext 111 112 /** 113 * Rename: allocate free physical register and update rename table 114 */ 115 val uops = Wire(Vec(RenameWidth, new MicroOp)) 116 uops.foreach( uop => { 117 uop.srcState := DontCare 118 uop.robIdx := DontCare 119 uop.debugInfo := DontCare 120 uop.lqIdx := DontCare 121 uop.sqIdx := DontCare 122 }) 123 124 require(RenameWidth >= CommitWidth) 125 val needVecDest = Wire(Vec(RenameWidth, Bool())) 126 val needFpDest = Wire(Vec(RenameWidth, Bool())) 127 val needIntDest = Wire(Vec(RenameWidth, Bool())) 128 val needNotIntDest = Wire(Vec(RenameWidth, Bool())) 129 val hasValid = Cat(io.in.map(_.valid)).orR 130 131 val isMove = io.in.map(_.bits.ctrl.isMove) 132 133 val walkNeedNotIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 134 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 135 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 136 137 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 138 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 139 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 140 141 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 142 143 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 144 145 // uop calculation 146 for (i <- 0 until RenameWidth) { 147 uops(i).cf := io.in(i).bits.cf 148 uops(i).ctrl := io.in(i).bits.ctrl 149 150 // update cf according to ssit result 151 uops(i).cf.storeSetHit := io.ssit(i).valid 152 uops(i).cf.loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 153 uops(i).cf.ssid := io.ssit(i).ssid 154 155 // update cf according to waittable result 156 uops(i).cf.loadWaitBit := io.waittable(i) 157 158 // alloc a new phy reg, fp and vec share the `fpFreeList` 159 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 160 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 161 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 162 needNotIntDest(i) := io.in(i).valid && needDestReg(int = false, io.in(i).bits) 163 if (i < CommitWidth) { 164 walkNeedNotIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(int = false, io.robCommits.info(i)) 165 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(int = true, io.robCommits.info(i)) 166 walkIsMove(i) := io.robCommits.info(i).isMove 167 } 168 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedNotIntDest(i), needNotIntDest(i)) 169 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 170 171 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 172 io.in(i).ready := !hasValid || canOut 173 174 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 175 176 uops(i).psrc(0) := Mux1H(uops(i).ctrl.srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 177 uops(i).psrc(1) := Mux1H(uops(i).ctrl.srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 178 // int psrc2 should be bypassed from next instruction if it is fused 179 if (i < RenameWidth - 1) { 180 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 181 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 182 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 183 uops(i).psrc(1) := 0.U 184 } 185 } 186 uops(i).psrc(2) := Mux1H(uops(i).ctrl.srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 187 uops(i).psrc(3) := io.vecReadPorts(i)(3) 188 uops(i).old_pdest := Mux1H(Seq( 189 uops(i).ctrl.rfWen -> io.intReadPorts(i).last, 190 uops(i).ctrl.fpWen -> io.fpReadPorts (i).last, 191 uops(i).ctrl.vecWen -> io.vecReadPorts(i).last 192 )) 193 uops(i).eliminatedMove := isMove(i) 194 195 // update pdest 196 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 197 // normal fp inst 198 Mux(needNotIntDest(i), fpFreeList.io.allocatePhyReg(i), 199 /* default */0.U)) 200 201 // Assign performance counters 202 uops(i).debugInfo.renameTime := GTimer() 203 204 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 205 io.out(i).bits := uops(i) 206 // dirty code for fence. The lsrc is passed by imm. 207 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 208 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 209 } 210 // dirty code for vsetvl(11)/vsetvli(15). The lsrc0 is passed by imm. 211 val isVsetvl_ = FuType.isIntExu(io.in(i).bits.ctrl.fuType) && (ALUOpType.isVsetvli(io.in(i).bits.ctrl.fuOpType) || ALUOpType.isVsetvl(io.in(i).bits.ctrl.fuOpType)) 212 when (isVsetvl_){ 213 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(0).orR.asUInt, io.in(i).bits.ctrl.imm(14,0)) // lsrc(0) Not Zero 214 } 215 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 216 when (io.in(i).bits.ctrl.isSoftPrefetch) { 217 io.out(i).bits.ctrl.fuType := FuType.ldu 218 io.out(i).bits.ctrl.fuOpType := Mux(io.in(i).bits.ctrl.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 219 io.out(i).bits.ctrl.selImm := SelImm.IMM_S 220 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.imm(io.in(i).bits.ctrl.imm.getWidth - 1, 5), 0.U(5.W)) 221 } 222 223 // write speculative rename table 224 // we update rat later inside commit code 225 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 226 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 227 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 228 229 if (i < CommitWidth) { 230 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 231 walkPdest(i) := io.robCommits.info(i).pdest 232 } else { 233 walkPdest(i) := io.out(i).bits.pdest 234 } 235 236 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 237 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 238 } 239 240 /** 241 * How to set psrc: 242 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 243 * - default: psrc from RAT 244 * How to set pdest: 245 * - Mux(isMove, psrc, pdest_from_freelist). 246 * 247 * The critical path of rename lies here: 248 * When move elimination is enabled, we need to update the rat with psrc. 249 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 250 * 251 * If we expand these logic for pdest(N): 252 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 253 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 254 * Mux(bypass(N, N - 2), pdest(N - 2), 255 * ... 256 * Mux(bypass(N, 0), pdest(0), 257 * rat_out(N))...)), 258 * freelist_out(N)) 259 */ 260 // a simple functional model for now 261 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 262 val bypassCond = Wire(Vec(5, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 263 for (i <- 1 until RenameWidth) { 264 val vecCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 265 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 266 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 267 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 268 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 269 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 270 val indexMatch = in.bits.ctrl.ldest === t 271 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 272 indexMatch && writeMatch 273 } 274 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 275 } 276 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 277 (z, next) => Mux(next._2, next._1, z) 278 } 279 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 280 (z, next) => Mux(next._2, next._1, z) 281 } 282 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 283 (z, next) => Mux(next._2, next._1, z) 284 } 285 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 286 (z, next) => Mux(next._2, next._1, z) 287 } 288 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).old_pdest) { 289 (z, next) => Mux(next._2, next._1, z) 290 } 291 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 292 293 // For fused-lui-load, load.src(0) is replaced by the imm. 294 val last_is_lui = io.in(i - 1).bits.ctrl.selImm === SelImm.IMM_U && io.in(i - 1).bits.ctrl.srcType(0) =/= SrcType.pc 295 val this_is_load = io.in(i).bits.ctrl.fuType === FuType.ldu 296 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 297 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 298 when (fused_lui_load) { 299 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 300 val lui_imm = io.in(i - 1).bits.ctrl.imm 301 val ld_imm = io.in(i).bits.ctrl.imm 302 io.out(i).bits.ctrl.srcType(0) := SrcType.imm 303 io.out(i).bits.ctrl.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 304 val psrcWidth = uops(i).psrc.head.getWidth 305 val lui_imm_in_imm = uops(i).ctrl.imm.getWidth - Imm_I().len 306 val left_lui_imm = Imm_U().len - lui_imm_in_imm 307 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 308 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 309 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 310 } 311 312 } 313 314 /** 315 * Instructions commit: update freelist and rename table 316 */ 317 for (i <- 0 until CommitWidth) { 318 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 319 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 320 321 // I. RAT Update 322 // When redirect happens (mis-prediction), don't update the rename table 323 io.intRenamePorts(i).wen := intSpecWen(i) 324 io.intRenamePorts(i).addr := uops(i).ctrl.ldest 325 io.intRenamePorts(i).data := io.out(i).bits.pdest 326 327 io.fpRenamePorts(i).wen := fpSpecWen(i) 328 io.fpRenamePorts(i).addr := uops(i).ctrl.ldest 329 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 330 331 io.vecRenamePorts(i).wen := vecSpecWen(i) 332 io.vecRenamePorts(i).addr := uops(i).ctrl.ldest 333 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 334 335 // II. Free List Update 336 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 337 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 338 fpFreeList.io.freeReq(i) := commitValid && needDestRegCommit(int = false, io.robCommits.info(i)) 339 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 340 341 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(int = true, io.robCommits.info(i)) && !io.robCommits.isWalk 342 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 343 } 344 345 when(io.robCommits.isWalk) { 346 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 347 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 348 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 349 } 350 } 351 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 352 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 353 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 354 } 355 } 356 } 357 358 /* 359 Debug and performance counters 360 */ 361 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 362 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 363 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 364 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 365 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 366 p"lsrc(3):${in.bits.ctrl.lsrc(3)} -> psrc(3):${out.bits.psrc(3)} " + 367 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 368 p"old_pdest:${out.bits.old_pdest}\n" 369 ) 370 } 371 372 for ((x,y) <- io.in.zip(io.out)) { 373 printRenameInfo(x, y) 374 } 375 376 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 377 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 378 for (i <- 0 until CommitWidth) { 379 val info = io.robCommits.info(i) 380 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 381 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}" + 382 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 383 } 384 385 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 386 387 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 388 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 389 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 390 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 391 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 392 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 393 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 394 XSPerfAccumulate("recovery_bubbles", PopCount(io.in.map(_.valid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk))) 395 396 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.ctrl.isMove))) 397 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.ctrl.fuType === FuType.ldu && o.bits.ctrl.srcType(0) === SrcType.imm) 398 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 399 400 val renamePerf = Seq( 401 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 402 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 403 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 404 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 405 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 406 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 407 ) 408 val intFlPerf = intFreeList.getPerfEvents 409 val fpFlPerf = fpFreeList.getPerfEvents 410 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 411 generatePerfEvent() 412} 413