1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.rename.freelist._ 27import xiangshan.mem.mdp._ 28 29class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 30 val io = IO(new Bundle() { 31 val redirect = Flipped(ValidIO(new Redirect)) 32 val robCommits = Input(new RobCommitIO) 33 // from decode 34 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 35 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 36 // ssit read result 37 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 38 // waittable read result 39 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 40 // to rename table 41 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 42 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 43 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 44 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 45 // to dispatch1 46 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 47 // debug arch ports 48 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 49 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 50 }) 51 52 // create free list and rat 53 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 54 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 55 val fpFreeList = Module(new StdFreeList(NRPhyRegs - 32)) 56 57 intRefCounter.io.commit <> io.robCommits 58 intRefCounter.io.redirect := io.redirect.valid 59 intRefCounter.io.debug_int_rat <> io.debug_int_rat 60 intFreeList.io.commit <> io.robCommits 61 intFreeList.io.debug_rat <> io.debug_int_rat 62 fpFreeList.io.commit <> io.robCommits 63 fpFreeList.io.debug_rat <> io.debug_fp_rat 64 65 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 66 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 67 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 68 } 69 def needDestRegCommit[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 70 if(fp) x.fpWen else x.rfWen 71 } 72 def needDestRegWalk[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 73 if(fp) x.fpWen else x.rfWen && x.ldest =/= 0.U 74 } 75 76 // connect [redirect + walk] ports for __float point__ & __integer__ free list 77 Seq((fpFreeList, true), (intFreeList, false)).foreach{ case (fl, isFp) => 78 fl.io.redirect := io.redirect.valid 79 fl.io.walk := io.robCommits.isWalk 80 } 81 // only when both fp and int free list and dispatch1 has enough space can we do allocation 82 // when isWalk, freelist can definitely allocate 83 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 84 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 85 86 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 87 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 88 89 90 // speculatively assign the instruction with an robIdx 91 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 92 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 93 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 94 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 95 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 96 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 97 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 98 robIdxHead := robIdxHeadNext 99 100 /** 101 * Rename: allocate free physical register and update rename table 102 */ 103 val uops = Wire(Vec(RenameWidth, new MicroOp)) 104 uops.foreach( uop => { 105 uop.srcState(0) := DontCare 106 uop.srcState(1) := DontCare 107 uop.srcState(2) := DontCare 108 uop.robIdx := DontCare 109 uop.debugInfo := DontCare 110 uop.lqIdx := DontCare 111 uop.sqIdx := DontCare 112 }) 113 114 require(RenameWidth >= CommitWidth) 115 116 val needFpDest = Wire(Vec(RenameWidth, Bool())) 117 val needIntDest = Wire(Vec(RenameWidth, Bool())) 118 val hasValid = Cat(io.in.map(_.valid)).orR 119 120 val isMove = io.in.map(_.bits.ctrl.isMove) 121 122 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 123 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 124 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 125 126 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 127 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 128 129 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 130 131 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 132 133 // uop calculation 134 for (i <- 0 until RenameWidth) { 135 uops(i).cf := io.in(i).bits.cf 136 uops(i).ctrl := io.in(i).bits.ctrl 137 138 // update cf according to ssit result 139 uops(i).cf.storeSetHit := io.ssit(i).valid 140 uops(i).cf.loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 141 uops(i).cf.ssid := io.ssit(i).ssid 142 143 // update cf according to waittable result 144 uops(i).cf.loadWaitBit := io.waittable(i) 145 146 // alloc a new phy reg 147 needFpDest(i) := io.in(i).valid && needDestReg(fp = true, io.in(i).bits) 148 needIntDest(i) := io.in(i).valid && needDestReg(fp = false, io.in(i).bits) 149 if (i < CommitWidth) { 150 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(fp = true, io.robCommits.info(i)) 151 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(fp = false, io.robCommits.info(i)) 152 walkIsMove(i) := io.robCommits.info(i).isMove 153 } 154 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedFpDest(i), needFpDest(i)) 155 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 156 157 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 158 io.in(i).ready := !hasValid || canOut 159 160 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 161 162 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, io.intReadPorts(i)(0), io.fpReadPorts(i)(0)) 163 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, io.intReadPorts(i)(1), io.fpReadPorts(i)(1)) 164 // int psrc2 should be bypassed from next instruction if it is fused 165 if (i < RenameWidth - 1) { 166 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 167 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 168 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 169 uops(i).psrc(1) := 0.U 170 } 171 } 172 uops(i).psrc(2) := io.fpReadPorts(i)(2) 173 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, io.intReadPorts(i).last, io.fpReadPorts(i).last) 174 uops(i).eliminatedMove := isMove(i) 175 176 // update pdest 177 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 178 // normal fp inst 179 Mux(needFpDest(i), fpFreeList.io.allocatePhyReg(i), 180 /* default */0.U)) 181 182 // Assign performance counters 183 uops(i).debugInfo.renameTime := GTimer() 184 185 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 186 io.out(i).bits := uops(i) 187 // dirty code for fence. The lsrc is passed by imm. 188 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 189 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 190 } 191 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 192 when (io.in(i).bits.ctrl.isSoftPrefetch) { 193 io.out(i).bits.ctrl.fuType := FuType.ldu 194 io.out(i).bits.ctrl.fuOpType := Mux(io.in(i).bits.ctrl.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 195 io.out(i).bits.ctrl.selImm := SelImm.IMM_S 196 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.imm(io.in(i).bits.ctrl.imm.getWidth - 1, 5), 0.U(5.W)) 197 } 198 199 // write speculative rename table 200 // we update rat later inside commit code 201 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 202 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 203 204 if (i < CommitWidth) { 205 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 206 walkPdest(i) := io.robCommits.info(i).pdest 207 } else { 208 walkPdest(i) := io.out(i).bits.pdest 209 } 210 211 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 212 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 213 } 214 215 /** 216 * How to set psrc: 217 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 218 * - default: psrc from RAT 219 * How to set pdest: 220 * - Mux(isMove, psrc, pdest_from_freelist). 221 * 222 * The critical path of rename lies here: 223 * When move elimination is enabled, we need to update the rat with psrc. 224 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 225 * 226 * If we expand these logic for pdest(N): 227 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 228 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 229 * Mux(bypass(N, N - 2), pdest(N - 2), 230 * ... 231 * Mux(bypass(N, 0), pdest(0), 232 * rat_out(N))...)), 233 * freelist_out(N)) 234 */ 235 // a simple functional model for now 236 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 237 val bypassCond = Wire(Vec(4, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 238 for (i <- 1 until RenameWidth) { 239 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 240 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 241 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 242 for ((((cond1, cond2), t), j) <- fpCond.zip(intCond).zip(target).zipWithIndex) { 243 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 244 val indexMatch = in.bits.ctrl.ldest === t 245 val writeMatch = cond2 && needIntDest(j) || cond1 && needFpDest(j) 246 indexMatch && writeMatch 247 } 248 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 249 } 250 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 251 (z, next) => Mux(next._2, next._1, z) 252 } 253 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 254 (z, next) => Mux(next._2, next._1, z) 255 } 256 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 257 (z, next) => Mux(next._2, next._1, z) 258 } 259 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).old_pdest) { 260 (z, next) => Mux(next._2, next._1, z) 261 } 262 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 263 264 // For fused-lui-load, load.src(0) is replaced by the imm. 265 val last_is_lui = io.in(i - 1).bits.ctrl.selImm === SelImm.IMM_U && io.in(i - 1).bits.ctrl.srcType(0) =/= SrcType.pc 266 val this_is_load = io.in(i).bits.ctrl.fuType === FuType.ldu 267 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 268 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 269 when (fused_lui_load) { 270 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 271 val lui_imm = io.in(i - 1).bits.ctrl.imm 272 val ld_imm = io.in(i).bits.ctrl.imm 273 io.out(i).bits.ctrl.srcType(0) := SrcType.imm 274 io.out(i).bits.ctrl.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 275 val psrcWidth = uops(i).psrc.head.getWidth 276 val lui_imm_in_imm = uops(i).ctrl.imm.getWidth - Imm_I().len 277 val left_lui_imm = Imm_U().len - lui_imm_in_imm 278 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 279 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 280 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 281 } 282 283 } 284 285 /** 286 * Instructions commit: update freelist and rename table 287 */ 288 for (i <- 0 until CommitWidth) { 289 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 290 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 291 292 Seq((io.intRenamePorts, false), (io.fpRenamePorts, true)) foreach { case (rat, fp) => 293 /* 294 I. RAT Update 295 */ 296 297 // walk back write - restore spec state : ldest => old_pdest 298 if (fp && i < RenameWidth) { 299 // When redirect happens (mis-prediction), don't update the rename table 300 rat(i).wen := fpSpecWen(i) 301 rat(i).addr := uops(i).ctrl.ldest 302 rat(i).data := fpFreeList.io.allocatePhyReg(i) 303 } else if (!fp && i < RenameWidth) { 304 rat(i).wen := intSpecWen(i) 305 rat(i).addr := uops(i).ctrl.ldest 306 rat(i).data := io.out(i).bits.pdest 307 } 308 309 /* 310 II. Free List Update 311 */ 312 if (fp) { // Float Point free list 313 fpFreeList.io.freeReq(i) := commitValid && needDestRegCommit(fp, io.robCommits.info(i)) 314 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 315 } else { // Integer free list 316 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 317 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 318 } 319 } 320 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(false, io.robCommits.info(i)) && !io.robCommits.isWalk 321 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 322 } 323 324 when(io.robCommits.isWalk) { 325 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 326 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 327 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 328 } 329 } 330 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 331 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 332 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 333 } 334 } 335 } 336 337 /* 338 Debug and performance counters 339 */ 340 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 341 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 342 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 343 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 344 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 345 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 346 p"old_pdest:${out.bits.old_pdest}\n" 347 ) 348 } 349 350 for((x,y) <- io.in.zip(io.out)){ 351 printRenameInfo(x, y) 352 } 353 354 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 355 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 356 for (i <- 0 until CommitWidth) { 357 val info = io.robCommits.info(i) 358 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 359 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " + 360 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 361 } 362 363 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 364 365 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 366 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 367 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 368 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 369 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 370 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 371 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 372 XSPerfAccumulate("recovery_bubbles", PopCount(io.in.map(_.valid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk))) 373 374 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.ctrl.isMove))) 375 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.ctrl.fuType === FuType.ldu && o.bits.ctrl.srcType(0) === SrcType.imm) 376 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 377 378 379 val renamePerf = Seq( 380 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 381 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 382 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 383 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 384 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 385 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 386 ) 387 val intFlPerf = intFreeList.getPerfEvents 388 val fpFlPerf = fpFreeList.getPerfEvents 389 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 390 generatePerfEvent() 391} 392