1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31import xiangshan.ExceptionNO._ 32 33class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 34 35 // params alias 36 private val numRegSrc = backendParams.numRegSrc 37 private val numVecRegSrc = backendParams.numVecRegSrc 38 private val numVecRatPorts = numVecRegSrc 39 40 println(s"[Rename] numRegSrc: $numRegSrc") 41 42 val io = IO(new Bundle() { 43 val redirect = Flipped(ValidIO(new Redirect)) 44 val rabCommits = Input(new RabCommitIO) 45 // from decode 46 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 47 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 48 // ssit read result 49 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 50 // waittable read result 51 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 52 // to rename table 53 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 54 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 55 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 56 val v0ReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 57 val vlReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 58 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 59 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 60 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 61 val v0RenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 62 val vlRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 63 // from rename table 64 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 65 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 66 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 67 val v0_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 68 val vl_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 69 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 70 // to dispatch1 71 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 72 // for snapshots 73 val snpt = Input(new SnapshotPort) 74 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 75 val snptIsFull= Input(Bool()) 76 // debug arch ports 77 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 78 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 79 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Input(UInt(PhyRegIdxWidth.W)))) else None 80 val debug_v0_rat = if (backendParams.debugEn) Some(Input(UInt(PhyRegIdxWidth.W))) else None 81 val debug_vl_rat = if (backendParams.debugEn) Some(Input(UInt(PhyRegIdxWidth.W))) else None 82 // perf only 83 val stallReason = new Bundle { 84 val in = Flipped(new StallReasonIO(RenameWidth)) 85 val out = new StallReasonIO(RenameWidth) 86 } 87 }) 88 89 // io alias 90 private val dispatchCanAcc = io.out.head.ready 91 92 val compressUnit = Module(new CompressUnit()) 93 // create free list and rat 94 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 95 val fpFreeList = Module(new StdFreeList(FpPhyRegs - FpLogicRegs, FpLogicRegs, Reg_F)) 96 val vecFreeList = Module(new StdFreeList(VfPhyRegs - VecLogicRegs, VecLogicRegs, Reg_V)) 97// val v0FreeList = Module(new StdFreeList(V0PhyRegs - V0LogicRegs, V0LogicRegs, Reg_V0)) 98// val vlFreeList = Module(new StdFreeList(VlPhyRegs - VlLogicRegs, VlLogicRegs, Reg_Vl)) 99 val v0FreeList = Module(new StdFreeList(21, 1, Reg_V0)) 100 val vlFreeList = Module(new StdFreeList(31, 2, Reg_Vl)) 101 102 103 intFreeList.io.commit <> io.rabCommits 104 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 105 fpFreeList.io.commit <> io.rabCommits 106 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 107 vecFreeList.io.commit <> io.rabCommits 108 vecFreeList.io.debug_rat.foreach(_ <> io.debug_vec_rat.get) 109 v0FreeList.io.commit <> io.rabCommits 110 v0FreeList.io.debug_rat.foreach(_ <> io.debug_v0_rat.get) 111 vlFreeList.io.commit <> io.rabCommits 112 vlFreeList.io.debug_rat.foreach(_ <> io.debug_vl_rat.get) 113 114 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 115 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 116 case Reg_I => x.rfWen && x.ldest =/= 0.U 117 case Reg_F => x.fpWen 118 case Reg_V => x.vecWen 119 case Reg_V0 => x.v0Wen 120 case Reg_Vl => x.vlWen 121 } 122 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 123 reg_t match { 124 case Reg_I => x.rfWen 125 case Reg_F => x.fpWen 126 case Reg_V => x.vecWen 127 case Reg_V0 => x.v0Wen 128 case Reg_Vl => x.vlWen 129 } 130 } 131 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 132 reg_t match { 133 case Reg_I => x.rfWen && x.ldest =/= 0.U 134 case Reg_F => x.fpWen 135 case Reg_V => x.vecWen 136 case Reg_V0 => x.v0Wen 137 case Reg_Vl => x.vlWen 138 } 139 } 140 141 // connect [redirect + walk] ports for fp & vec & int free list 142 Seq(fpFreeList, vecFreeList, intFreeList, v0FreeList, vlFreeList).foreach { case fl => 143 fl.io.redirect := io.redirect.valid 144 fl.io.walk := io.rabCommits.isWalk 145 } 146 // only when all free list and dispatch1 has enough space can we do allocation 147 // when isWalk, freelist can definitely allocate 148 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 149 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 150 vecFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 151 v0FreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 152 vlFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 153 154 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ vec free list ready ++ not walk 155 val canOut = dispatchCanAcc && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 156 157 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 158 sink.valid := source.valid 159 sink.bits := source.bits 160 } 161 val needRobFlags = compressUnit.io.out.needRobFlags 162 val instrSizesVec = compressUnit.io.out.instrSizes 163 val compressMasksVec = compressUnit.io.out.masks 164 165 // speculatively assign the instruction with an robIdx 166 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 167 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 168 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 169 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 170 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 171 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 172 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 173 robIdxHead := robIdxHeadNext 174 175 /** 176 * Rename: allocate free physical register and update rename table 177 */ 178 val uops = Wire(Vec(RenameWidth, new DynInst)) 179 uops.foreach( uop => { 180 uop.srcState := DontCare 181 uop.debugInfo := DontCare 182 uop.lqIdx := DontCare 183 uop.sqIdx := DontCare 184 uop.waitForRobIdx := DontCare 185 uop.singleStep := DontCare 186 uop.snapshot := DontCare 187 uop.srcLoadDependency := DontCare 188 uop.numLsElem := DontCare 189 uop.hasException := DontCare 190 }) 191 192 val needVecDest = Wire(Vec(RenameWidth, Bool())) 193 val needFpDest = Wire(Vec(RenameWidth, Bool())) 194 val needIntDest = Wire(Vec(RenameWidth, Bool())) 195 val needV0Dest = Wire(Vec(RenameWidth, Bool())) 196 val needVlDest = Wire(Vec(RenameWidth, Bool())) 197 val hasValid = Cat(io.in.map(_.valid)).orR 198 private val inHeadValid = io.in.head.valid 199 200 val isMove = Wire(Vec(RenameWidth, Bool())) 201 isMove zip io.in.map(_.bits) foreach { 202 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 203 } 204 205 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 206 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 207 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 208 val walkNeedV0Dest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 209 val walkNeedVlDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 210 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 211 212 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 213 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 214 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 215 val v0SpecWen = Wire(Vec(RenameWidth, Bool())) 216 val vlSpecWen = Wire(Vec(RenameWidth, Bool())) 217 218 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 219 220 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 221 222 // uop calculation 223 for (i <- 0 until RenameWidth) { 224 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 225 226 // update cf according to ssit result 227 uops(i).storeSetHit := io.ssit(i).valid 228 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 229 uops(i).ssid := io.ssit(i).ssid 230 231 // update cf according to waittable result 232 uops(i).loadWaitBit := io.waittable(i) 233 234 uops(i).replayInst := false.B // set by IQ or MemQ 235 // alloc a new phy reg 236 needV0Dest(i) := io.in(i).valid && needDestReg(Reg_V0, io.in(i).bits) 237 needVlDest(i) := io.in(i).valid && needDestReg(Reg_Vl, io.in(i).bits) 238 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 239 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 240 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 241 if (i < RabCommitWidth) { 242 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 243 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 244 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 245 walkNeedV0Dest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V0, io.rabCommits.info(i)) 246 walkNeedVlDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_Vl, io.rabCommits.info(i)) 247 walkIsMove(i) := io.rabCommits.info(i).isMove 248 } 249 fpFreeList.io.allocateReq(i) := needFpDest(i) 250 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) 251 vecFreeList.io.allocateReq(i) := needVecDest(i) 252 vecFreeList.io.walkReq(i) := walkNeedVecDest(i) 253 v0FreeList.io.allocateReq(i) := needV0Dest(i) 254 v0FreeList.io.walkReq(i) := walkNeedV0Dest(i) 255 vlFreeList.io.allocateReq(i) := needVlDest(i) 256 vlFreeList.io.walkReq(i) := walkNeedVlDest(i) 257 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 258 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 259 260 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 261 io.in(i).ready := !hasValid || canOut 262 263 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 264 uops(i).instrSize := instrSizesVec(i) 265 when(isMove(i)) { 266 uops(i).numUops := 0.U 267 uops(i).numWB := 0.U 268 } 269 if (i > 0) { 270 when(!needRobFlags(i - 1)) { 271 uops(i).firstUop := false.B 272 uops(i).ftqPtr := uops(i - 1).ftqPtr 273 uops(i).ftqOffset := uops(i - 1).ftqOffset 274 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 275 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 276 } 277 } 278 when(!needRobFlags(i)) { 279 uops(i).lastUop := false.B 280 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 281 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 282 } 283 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 284 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 285 // vector instructions' uopSplitType cannot be UopSplitType.SCA_SIM 286 uops(i).dirtyVs := (compressMasksVec(i) & Cat(io.in.map(_.bits.uopSplitType =/= UopSplitType.SCA_SIM).reverse)).orR 287 // psrc0,psrc1,psrc2 don't require v0ReadPorts because their srcType can distinguish whether they are V0 or not 288 uops(i).psrc(0) := Mux1H(uops(i).srcType(0)(2, 0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 289 uops(i).psrc(1) := Mux1H(uops(i).srcType(1)(2, 0), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 290 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 291 uops(i).psrc(3) := io.v0ReadPorts(i)(0) 292 uops(i).psrc(4) := io.vlReadPorts(i)(0) 293 294 // int psrc2 should be bypassed from next instruction if it is fused 295 if (i < RenameWidth - 1) { 296 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 297 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 298 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 299 uops(i).psrc(1) := 0.U 300 } 301 } 302 uops(i).eliminatedMove := isMove(i) 303 304 // update pdest 305 uops(i).pdest := MuxCase(0.U, Seq( 306 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 307 needFpDest(i) -> fpFreeList.io.allocatePhyReg(i), 308 needVecDest(i) -> vecFreeList.io.allocatePhyReg(i), 309 needV0Dest(i) -> v0FreeList.io.allocatePhyReg(i), 310 needVlDest(i) -> vlFreeList.io.allocatePhyReg(i), 311 )) 312 313 // Assign performance counters 314 uops(i).debugInfo.renameTime := GTimer() 315 316 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 317 io.out(i).bits := uops(i) 318 // Todo: move these shit in decode stage 319 // dirty code for fence. The lsrc is passed by imm. 320 when (io.out(i).bits.fuType === FuType.fence.U) { 321 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 322 } 323 324 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 325// when (io.in(i).bits.isSoftPrefetch) { 326// io.out(i).bits.fuType := FuType.ldu.U 327// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 328// io.out(i).bits.selImm := SelImm.IMM_S 329// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 330// } 331 332 // dirty code for lui+addi(w) fusion 333 if (i < RenameWidth - 1) { 334 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 335 when (fused_lui32) { 336 val lui_imm = io.in(i).bits.imm(19, 0) 337 val add_imm = io.in(i + 1).bits.imm(11, 0) 338 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 339 io.out(i).bits.imm := Cat(lui_imm, add_imm) 340 } 341 } 342 343 // write speculative rename table 344 // we update rat later inside commit code 345 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 346 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 347 vecSpecWen(i) := needVecDest(i) && vecFreeList.io.canAllocate && vecFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 348 v0SpecWen(i) := needV0Dest(i) && v0FreeList.io.canAllocate && v0FreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 349 vlSpecWen(i) := needVlDest(i) && vlFreeList.io.canAllocate && vlFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 350 351 352 if (i < RabCommitWidth) { 353 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 354 walkPdest(i) := io.rabCommits.info(i).pdest 355 } else { 356 walkPdest(i) := io.out(i).bits.pdest 357 } 358 } 359 360 /** 361 * How to set psrc: 362 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 363 * - default: psrc from RAT 364 * How to set pdest: 365 * - Mux(isMove, psrc, pdest_from_freelist). 366 * 367 * The critical path of rename lies here: 368 * When move elimination is enabled, we need to update the rat with psrc. 369 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 370 * 371 * If we expand these logic for pdest(N): 372 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 373 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 374 * Mux(bypass(N, N - 2), pdest(N - 2), 375 * ... 376 * Mux(bypass(N, 0), pdest(0), 377 * rat_out(N))...)), 378 * freelist_out(N)) 379 */ 380 // a simple functional model for now 381 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 382 383 // psrc(n) + pdest(1) 384 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 385 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 386 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 387 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 388 for (i <- 1 until RenameWidth) { 389 val v0Cond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 390 if (i == 3) (s === SrcType.vp) || (s === SrcType.v0) 391 else false.B 392 } :+ needV0Dest(i) 393 val vlCond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 394 if (i == 4) s === SrcType.vp 395 else false.B 396 } :+ needVlDest(i) 397 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 398 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 399 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 400 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 401 for ((((((cond1, (condV0, condVl)), cond2), cond3), t), j) <- vecCond.zip(v0Cond.zip(vlCond)).zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 402 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 403 val indexMatch = in.bits.ldest === t 404 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 405 val v0vlMatch = condV0 && needV0Dest(j) || condVl && needVlDest(j) 406 indexMatch && writeMatch || v0vlMatch 407 } 408 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 409 } 410 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 411 (z, next) => Mux(next._2, next._1, z) 412 } 413 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 414 (z, next) => Mux(next._2, next._1, z) 415 } 416 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 417 (z, next) => Mux(next._2, next._1, z) 418 } 419 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 420 (z, next) => Mux(next._2, next._1, z) 421 } 422 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 423 (z, next) => Mux(next._2, next._1, z) 424 } 425 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 426 427 // Todo: better implementation for fields reuse 428 // For fused-lui-load, load.src(0) is replaced by the imm. 429 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 430 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 431 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 432 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 433 when (fused_lui_load) { 434 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 435 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 436 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 437 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 438 io.out(i).bits.srcType(0) := SrcType.imm 439 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 440 } 441 442 } 443 444 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 445 val lastCycleCreateSnpt = RegInit(false.B) 446 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 447 val sameSnptDistance = (RobCommitWidth * 4).U 448 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 449 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 450 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 451 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 452 io.out.map{ x => 453 x.bits.hasException := Cat(selectFrontend(x.bits.exceptionVec) :+ x.bits.exceptionVec(illegalInstr) :+ x.bits.exceptionVec(virtualInstr)).orR || x.bits.trigger.getFrontendCanFire 454 } 455 if(backendParams.debugEn){ 456 dontTouch(robIdxHeadNext) 457 dontTouch(notInSameSnpt) 458 dontTouch(genSnapshot) 459 } 460 intFreeList.io.snpt := io.snpt 461 fpFreeList.io.snpt := io.snpt 462 vecFreeList.io.snpt := io.snpt 463 v0FreeList.io.snpt := io.snpt 464 vlFreeList.io.snpt := io.snpt 465 intFreeList.io.snpt.snptEnq := genSnapshot 466 fpFreeList.io.snpt.snptEnq := genSnapshot 467 vecFreeList.io.snpt.snptEnq := genSnapshot 468 v0FreeList.io.snpt.snptEnq := genSnapshot 469 vlFreeList.io.snpt.snptEnq := genSnapshot 470 471 /** 472 * Instructions commit: update freelist and rename table 473 */ 474 for (i <- 0 until RabCommitWidth) { 475 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 476 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 477 478 // I. RAT Update 479 // When redirect happens (mis-prediction), don't update the rename table 480 io.intRenamePorts(i).wen := intSpecWen(i) 481 io.intRenamePorts(i).addr := uops(i).ldest 482 io.intRenamePorts(i).data := io.out(i).bits.pdest 483 484 io.fpRenamePorts(i).wen := fpSpecWen(i) 485 io.fpRenamePorts(i).addr := uops(i).ldest 486 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 487 488 io.vecRenamePorts(i).wen := vecSpecWen(i) 489 io.vecRenamePorts(i).addr := uops(i).ldest 490 io.vecRenamePorts(i).data := vecFreeList.io.allocatePhyReg(i) 491 492 io.v0RenamePorts(i).wen := v0SpecWen(i) 493 io.v0RenamePorts(i).addr := uops(i).ldest 494 io.v0RenamePorts(i).data := v0FreeList.io.allocatePhyReg(i) 495 496 io.vlRenamePorts(i).wen := vlSpecWen(i) 497 io.vlRenamePorts(i).addr := uops(i).ldest 498 io.vlRenamePorts(i).data := vlFreeList.io.allocatePhyReg(i) 499 500 // II. Free List Update 501 intFreeList.io.freeReq(i) := io.int_need_free(i) 502 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 503 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_F, io.rabCommits.info(i))) 504 fpFreeList.io.freePhyReg(i) := io.fp_old_pdest(i) 505 vecFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V, io.rabCommits.info(i))) 506 vecFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 507 v0FreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V0, io.rabCommits.info(i))) 508 v0FreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 509 vlFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_Vl, io.rabCommits.info(i))) 510 vlFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 511 } 512 513 /* 514 Debug and performance counters 515 */ 516 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 517 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 518 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 519 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 520 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 521 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 522 ) 523 } 524 525 for ((x,y) <- io.in.zip(io.out)) { 526 printRenameInfo(x, y) 527 } 528 529 io.out.map { case x => 530 when(x.valid && x.bits.rfWen){ 531 assert(x.bits.ldest =/= 0.U, "rfWen cannot be 1 when Int regfile ldest is 0") 532 } 533 } 534 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 535 // bad speculation 536 val recStall = io.redirect.valid || io.rabCommits.isWalk 537 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 538 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 539 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 540 XSPerfAccumulate("recovery_stall", recStall) 541 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 542 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 543 XSPerfAccumulate("other_recovery_stall", otherRecStall) 544 // freelist stall 545 val notRecStall = !io.out.head.valid && !recStall 546 val intFlStall = notRecStall && inHeadValid && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 547 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 548 val vecFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 549 val v0FlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 550 val vlFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 551 val multiFlStall = notRecStall && inHeadValid && (PopCount(Cat( 552 !intFreeList.io.canAllocate, 553 !fpFreeList.io.canAllocate, 554 !vecFreeList.io.canAllocate, 555 !v0FreeList.io.canAllocate, 556 !vlFreeList.io.canAllocate, 557 )) > 1.U) 558 // other stall 559 val otherStall = notRecStall && !intFlStall && !fpFlStall && !vecFlStall && !v0FlStall && !vlFlStall && !multiFlStall 560 561 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 562 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 563 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 564 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 565 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 566 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 567 intFlStall -> TopDownCounters.IntFlStall.id.U, 568 fpFlStall -> TopDownCounters.FpFlStall.id.U, 569 vecFlStall -> TopDownCounters.VecFlStall.id.U, 570 v0FlStall -> TopDownCounters.V0FlStall.id.U, 571 vlFlStall -> TopDownCounters.VlFlStall.id.U, 572 multiFlStall -> TopDownCounters.MultiFlStall.id.U, 573 ) 574 )) 575 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 576 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 577 } 578 579 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 580 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 581 for (i <- 0 until RabCommitWidth) { 582 val info = io.rabCommits.info(i) 583 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 584 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen} v0Wen:${info.v0Wen} vlWen:${info.vlWen}") 585 } 586 587 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 588 589 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 590 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 591 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 592 XSPerfAccumulate("wait_cycle", !io.in.head.valid && dispatchCanAcc) 593 594 // These stall reasons could overlap each other, but we configure the priority as fellows. 595 // walk stall > dispatch stall > int freelist stall > fp freelist stall 596 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 597 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 598 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc 599 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 600 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 601 private val stallForVecFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 602 private val stallForV0FL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 603 private val stallForVlFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 604 XSPerfAccumulate("stall_cycle", inHeadStall) 605 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 606 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 607 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 608 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 609 XSPerfAccumulate("stall_cycle_vec", stallForVecFL) 610 XSPerfAccumulate("stall_cycle_vec", stallForV0FL) 611 XSPerfAccumulate("stall_cycle_vec", stallForVlFL) 612 613 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 614 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 615 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 616 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 617 618 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 619 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 620 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 621 622 val renamePerf = Seq( 623 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 624 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 625 ("rename_stall ", inHeadStall), 626 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 627 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc), 628 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate), 629 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 630 ("rename_stall_cycle_vec ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate), 631 ("rename_stall_cycle_v0 ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate), 632 ("rename_stall_cycle_vl ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate), 633 ) 634 val intFlPerf = intFreeList.getPerfEvents 635 val fpFlPerf = fpFreeList.getPerfEvents 636 val vecFlPerf = vecFreeList.getPerfEvents 637 val v0FlPerf = v0FreeList.getPerfEvents 638 val vlFlPerf = vlFreeList.getPerfEvents 639 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf ++ v0FlPerf ++ vlFlPerf 640 generatePerfEvent() 641} 642