1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import xiangshan.backend.roq.RoqPtr 8 9class RenameBypassInfo extends XSBundle { 10 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 11 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 14} 15 16class Rename extends XSModule with HasCircularQueuePtrHelper { 17 val io = IO(new Bundle() { 18 val redirect = Flipped(ValidIO(new Redirect)) 19 val roqCommits = Flipped(new RoqCommitIO) 20 // from decode buffer 21 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 22 // to dispatch1 23 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 24 val renameBypass = Output(new RenameBypassInfo) 25 }) 26 27 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 28 XSInfo( 29 in.valid && in.ready, 30 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 31 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 32 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 33 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 34 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 35 p"old_pdest:${out.bits.old_pdest} " + 36 p"out v:${out.valid} r:${out.ready}\n" 37 ) 38 } 39 40 for((x,y) <- io.in.zip(io.out)){ 41 printRenameInfo(x, y) 42 } 43 44 val intFreeList, fpFreeList = Module(new FreeList).io 45 val intRat = Module(new RenameTable(float = false)).io 46 val fpRat = Module(new RenameTable(float = true)).io 47 val allPhyResource = Seq((intRat, intFreeList, false), (fpRat, fpFreeList, true)) 48 49 allPhyResource.map{ case (rat, freelist, _) => 50 rat.redirect := io.redirect 51 rat.walkWen := io.roqCommits.isWalk 52 freelist.redirect := io.redirect 53 freelist.walk.valid := io.roqCommits.isWalk 54 } 55 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 56 57 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 58 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 59 } 60 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 61 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 62 } 63 fpFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 64 intFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(false, i)}) 65 // walk has higher priority than allocation and thus we don't use isWalk here 66 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 67 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 68 69 // speculatively assign the instruction with an roqIdx 70 val validCount = PopCount(io.in.map(_.valid)) 71 val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr)) 72 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.isUnconditional() && !io.redirect.bits.flushItself()) 73 val roqIdxHeadNext = Mux(io.redirect.valid, 74 Mux(io.redirect.bits.isUnconditional(), 0.U.asTypeOf(new RoqPtr), io.redirect.bits.roqIdx), 75 Mux(lastCycleMisprediction, roqIdxHead + 1.U, Mux(canOut, roqIdxHead + validCount, roqIdxHead)) 76 ) 77 roqIdxHead := roqIdxHeadNext 78 79 /** 80 * Rename: allocate free physical register and update rename table 81 */ 82 val uops = Wire(Vec(RenameWidth, new MicroOp)) 83 84 uops.foreach( uop => { 85// uop.brMask := DontCare 86// uop.brTag := DontCare 87 uop.src1State := DontCare 88 uop.src2State := DontCare 89 uop.src3State := DontCare 90 uop.roqIdx := DontCare 91 uop.diffTestDebugLrScValid := DontCare 92 uop.debugInfo := DontCare 93 uop.lqIdx := DontCare 94 uop.sqIdx := DontCare 95 }) 96 97 val needFpDest = Wire(Vec(RenameWidth, Bool())) 98 val needIntDest = Wire(Vec(RenameWidth, Bool())) 99 val hasValid = Cat(io.in.map(_.valid)).orR 100 for (i <- 0 until RenameWidth) { 101 uops(i).cf := io.in(i).bits.cf 102 uops(i).ctrl := io.in(i).bits.ctrl 103 uops(i).brTag := io.in(i).bits.brTag 104 105 val inValid = io.in(i).valid 106 107 // alloc a new phy reg 108 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 109 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 110 fpFreeList.req.allocReqs(i) := needFpDest(i) 111 intFreeList.req.allocReqs(i) := needIntDest(i) 112 113 io.in(i).ready := !hasValid || canOut 114 115 // do checkpoints when a branch inst come 116 // for(fl <- Seq(fpFreeList, intFreeList)){ 117 // fl.cpReqs(i).valid := inValid 118 // fl.cpReqs(i).bits := io.in(i).bits.brTag 119 // } 120 121 uops(i).pdest := Mux(needIntDest(i), 122 intFreeList.req.pdests(i), 123 Mux( 124 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 125 0.U, fpFreeList.req.pdests(i) 126 ) 127 ) 128 129 uops(i).roqIdx := roqIdxHead + i.U 130 131 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 132 io.out(i).bits := uops(i) 133 134 // write speculative rename table 135 allPhyResource.map{ case (rat, freelist, _) => 136 val specWen = freelist.req.allocReqs(i) && freelist.req.canAlloc && freelist.req.doAlloc && !io.roqCommits.isWalk 137 138 rat.specWritePorts(i).wen := specWen 139 rat.specWritePorts(i).addr := uops(i).ctrl.ldest 140 rat.specWritePorts(i).wdata := freelist.req.pdests(i) 141 142 freelist.deallocReqs(i) := specWen 143 } 144 145 // read rename table 146 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 147 val rat = if(fp) fpRat else intRat 148 val srcCnt = lsrcList.size 149 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 150 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 151 for(k <- 0 until srcCnt+1){ 152 val rportIdx = i * (srcCnt+1) + k 153 if(k != srcCnt){ 154 rat.readPorts(rportIdx).addr := lsrcList(k) 155 psrcVec(k) := rat.readPorts(rportIdx).rdata 156 } else { 157 rat.readPorts(rportIdx).addr := ldest 158 old_pdest := rat.readPorts(rportIdx).rdata 159 } 160 } 161 (psrcVec, old_pdest) 162 } 163 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 164 val ldest = uops(i).ctrl.ldest 165 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 166 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 167 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 168 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 169 uops(i).psrc3 := fpPhySrcVec(2) 170 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 171 } 172 173 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 174 // Instead, we determine whether there're some dependences between the valid instructions. 175 for (i <- 1 until RenameWidth) { 176 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 177 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 178 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 179 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 180 }).reverse) 181 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 182 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 183 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 184 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 185 }).reverse) 186 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 187 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 188 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 189 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 190 }).reverse) 191 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 192 val fpMatch = needFpDest(j) && needFpDest(i) 193 val intMatch = needIntDest(j) && needIntDest(i) 194 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 195 }).reverse) 196 } 197 198 /** 199 * Instructions commit: update freelist and rename table 200 */ 201 for (i <- 0 until CommitWidth) { 202 if (i >= RenameWidth) { 203 allPhyResource.map{ case (rat, _, _) => 204 rat.specWritePorts(i).wen := false.B 205 rat.specWritePorts(i).addr := DontCare 206 rat.specWritePorts(i).wdata := DontCare 207 } 208 } 209 210 allPhyResource.map{ case (rat, freelist, fp) => 211 // walk back write 212 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 213 214 when (commitDestValid && io.roqCommits.isWalk) { 215 rat.specWritePorts(i).wen := true.B 216 rat.specWritePorts(i).addr := io.roqCommits.info(i).ldest 217 rat.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 218 XSInfo({if(fp) p"fp" else p"int "} + p"walk: " + 219 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n") 220 } 221 222 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 223 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 224 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 225 226 XSInfo(rat.archWritePorts(i).wen, 227 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 228 p" pdest:${rat.archWritePorts(i).wdata}\n" 229 ) 230 231 freelist.deallocReqs(i) := rat.archWritePorts(i).wen 232 freelist.deallocPregs(i) := io.roqCommits.info(i).old_pdest 233 } 234 } 235} 236