1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7class Rename extends XSModule { 8 val io = IO(new Bundle() { 9 val redirect = Flipped(ValidIO(new Redirect)) 10 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 11 val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 12 val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 13 val intRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 14 val fpRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 15 val intPregRdy = Vec(NRReadPorts, Output(Bool())) 16 val fpPregRdy = Vec(NRReadPorts, Output(Bool())) 17 // from decode buffer 18 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 19 // to dispatch1 20 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 21 }) 22 23 val fpFreeList, intFreeList = Module(new FreeList).io 24 val fpRat = Module(new RenameTable(float = true)).io 25 val intRat = Module(new RenameTable(float = false)).io 26 val fpBusyTable, intBusyTable = Module(new BusyTable).io 27 28 fpFreeList.redirect := io.redirect 29 intFreeList.redirect := io.redirect 30 31 val flush = io.redirect.valid && io.redirect.bits.isException 32 fpRat.flush := flush 33 intRat.flush := flush 34 fpBusyTable.flush := flush 35 intBusyTable.flush := flush 36 37 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 38 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 39 } 40 41 val uops = Wire(Vec(RenameWidth, new MicroOp)) 42 43 uops.foreach( uop => { 44 uop.brMask := DontCare 45 uop.brTag := DontCare 46 uop.src1State := DontCare 47 uop.src2State := DontCare 48 uop.src3State := DontCare 49 uop.roqIdx := DontCare 50 }) 51 52 var last_can_alloc = WireInit(true.B) 53 for(i <- 0 until RenameWidth){ 54 uops(i).cf := io.in(i).bits.cf 55 uops(i).ctrl := io.in(i).bits.ctrl 56 57 // alloc a new phy reg 58 val needFpDest = io.in(i).valid && needDestReg(fp = true, io.in(i).bits) 59 val needIntDest = io.in(i).valid && needDestReg(fp = false, io.in(i).bits) 60 fpFreeList.allocReqs(i) := needFpDest && last_can_alloc && io.out(i).ready 61 intFreeList.allocReqs(i) := needIntDest && last_can_alloc && io.out(i).ready 62 val fpCanAlloc = fpFreeList.canAlloc(i) 63 val intCanAlloc = intFreeList.canAlloc(i) 64 val this_can_alloc = Mux(needIntDest, intCanAlloc, fpCanAlloc) 65 io.in(i).ready := this_can_alloc 66 last_can_alloc = last_can_alloc && this_can_alloc 67 uops(i).pdest := Mux(needIntDest, intFreeList.pdests(i), fpFreeList.pdests(i)) 68 uops(i).freelistAllocPtr := Mux(needIntDest, intFreeList.allocPtrs(i), fpFreeList.allocPtrs(i)) 69 70 io.out(i).valid := io.in(i).fire() 71 io.out(i).bits := uops(i) 72 73 // write rename table 74 def writeRat(fp: Boolean) = { 75 val rat = if(fp) fpRat else intRat 76 val freeList = if(fp) fpFreeList else intFreeList 77 val busyTable = if(fp) fpBusyTable else intBusyTable 78 // speculative inst write 79 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 80 // walk back write 81 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 82 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 83 84 rat.specWritePorts(i).wen := specWen || walkWen 85 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 86 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 87 88 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 89 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 90 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 91 92 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 93 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 94 95 // set phy reg status to busy 96 busyTable.allocPregs(i).valid := specWen 97 busyTable.allocPregs(i).bits := freeList.pdests(i) 98 } 99 100 writeRat(fp = false) 101 writeRat(fp = true) 102 103 // read rename table 104 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 105 val rat = if(fp) fpRat else intRat 106 val srcCnt = lsrcList.size 107 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 108 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 109 for(k <- 0 until srcCnt+1){ 110 val rportIdx = i * (srcCnt+1) + k 111 if(k != srcCnt){ 112 rat.readPorts(rportIdx).addr := lsrcList(k) 113 psrcVec(k) := rat.readPorts(rportIdx).rdata 114 } else { 115 rat.readPorts(rportIdx).addr := ldest 116 old_pdest := rat.readPorts(rportIdx).rdata 117 } 118 } 119 (psrcVec, old_pdest) 120 } 121 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 122 val ldest = uops(i).ctrl.ldest 123 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 124 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 125 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 126 uops(i).psrc2 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 127 uops(i).psrc3 := fpPhySrcVec(2) 128 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 129 } 130 131 132 def updateBusyTable(fp: Boolean) = { 133 val wbResults = if(fp) io.wbFpResults else io.wbIntResults 134 val busyTable = if(fp) fpBusyTable else intBusyTable 135 for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs)){ 136 setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop) 137 setPhyRegRdy.bits := wb.bits.uop.pdest 138 } 139 } 140 141 updateBusyTable(false) 142 updateBusyTable(true) 143 144 intBusyTable.rfReadAddr <> io.intRfReadAddr 145 intBusyTable.pregRdy <> io.intPregRdy 146 fpBusyTable.rfReadAddr <> io.fpRfReadAddr 147 fpBusyTable.pregRdy <> io.fpPregRdy 148} 149