1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 26import xiangshan.backend.rob.RobPtr 27import xiangshan.backend.rename.freelist._ 28import xiangshan.mem.mdp._ 29 30class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 31 val io = IO(new Bundle() { 32 val redirect = Flipped(ValidIO(new Redirect)) 33 val robCommits = Input(new RobCommitIO) 34 // from decode 35 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 36 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 37 // ssit read result 38 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 39 // waittable read result 40 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 41 // to rename table 42 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 43 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 44 val vecReadPorts = Vec(RenameWidth, Vec(5, Input(UInt(PhyRegIdxWidth.W)))) 45 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 46 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 47 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 48 // to dispatch1 49 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 50 // debug arch ports 51 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 52 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 53 }) 54 55 // create free list and rat 56 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 57 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 58 val fpFreeList = Module(new StdFreeList(NRPhyRegs - 64)) 59 60 intRefCounter.io.commit <> io.robCommits 61 intRefCounter.io.redirect := io.redirect.valid 62 intRefCounter.io.debug_int_rat <> io.debug_int_rat 63 intFreeList.io.commit <> io.robCommits 64 intFreeList.io.debug_rat <> io.debug_int_rat 65 fpFreeList.io.commit <> io.robCommits 66 fpFreeList.io.debug_rat <> io.debug_fp_rat 67 68 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 69 // fp and vec share `fpFreeList` 70 def needDestReg[T <: CfCtrl](int: Boolean, x: T): Bool = { 71 if (int) x.ctrl.rfWen && x.ctrl.ldest =/= 0.U else x.ctrl.fpWen || x.ctrl.vecWen 72 } 73 def needDestReg[T <: CfCtrl](reg_t: RegType, x: T): Bool = reg_t match { 74 case Reg_I => x.ctrl.rfWen && x.ctrl.ldest =/= 0.U 75 case Reg_F => x.ctrl.fpWen 76 case Reg_V => x.ctrl.vecWen 77 } 78 def needDestRegCommit[T <: RobCommitInfo](int: Boolean, x: T): Bool = { 79 if (int) x.rfWen else x.fpWen || x.vecWen 80 } 81 def needDestRegWalk[T <: RobCommitInfo](int: Boolean, x: T): Bool = { 82 if(int) x.rfWen && x.ldest =/= 0.U else x.fpWen || x.vecWen 83 } 84 85 // connect [redirect + walk] ports for __float point__ & __integer__ free list 86 Seq(fpFreeList, intFreeList).foreach { case fl => 87 fl.io.redirect := io.redirect.valid 88 fl.io.walk := io.robCommits.isWalk 89 } 90 // only when both fp and int free list and dispatch1 has enough space can we do allocation 91 // when isWalk, freelist can definitely allocate 92 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 93 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 94 95 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 96 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 97 98 99 // speculatively assign the instruction with an robIdx 100 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 101 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 102 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 103 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 104 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 105 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 106 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 107 robIdxHead := robIdxHeadNext 108 109 /** 110 * Rename: allocate free physical register and update rename table 111 */ 112 val uops = Wire(Vec(RenameWidth, new MicroOp)) 113 uops.foreach( uop => { 114 uop.srcState := DontCare 115 uop.robIdx := DontCare 116 uop.debugInfo := DontCare 117 uop.lqIdx := DontCare 118 uop.sqIdx := DontCare 119 }) 120 121 require(RenameWidth >= CommitWidth) 122 val needVecDest = Wire(Vec(RenameWidth, Bool())) 123 val needFpDest = Wire(Vec(RenameWidth, Bool())) 124 val needIntDest = Wire(Vec(RenameWidth, Bool())) 125 val needNotIntDest = Wire(Vec(RenameWidth, Bool())) 126 val hasValid = Cat(io.in.map(_.valid)).orR 127 128 val isMove = io.in.map(_.bits.ctrl.isMove) 129 130 val walkNeedNotIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 131 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 132 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 133 134 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 135 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 136 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 137 138 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 139 140 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 141 142 // uop calculation 143 for (i <- 0 until RenameWidth) { 144 uops(i).cf := io.in(i).bits.cf 145 uops(i).ctrl := io.in(i).bits.ctrl 146 147 // update cf according to ssit result 148 uops(i).cf.storeSetHit := io.ssit(i).valid 149 uops(i).cf.loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 150 uops(i).cf.ssid := io.ssit(i).ssid 151 152 // update cf according to waittable result 153 uops(i).cf.loadWaitBit := io.waittable(i) 154 155 // alloc a new phy reg, fp and vec share the `fpFreeList` 156 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 157 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 158 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 159 needNotIntDest(i) := io.in(i).valid && needDestReg(int = false, io.in(i).bits) 160 if (i < CommitWidth) { 161 walkNeedNotIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(int = false, io.robCommits.info(i)) 162 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(int = true, io.robCommits.info(i)) 163 walkIsMove(i) := io.robCommits.info(i).isMove 164 } 165 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedNotIntDest(i), needNotIntDest(i)) 166 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 167 168 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 169 io.in(i).ready := !hasValid || canOut 170 171 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 172 173 uops(i).psrc(0) := Mux1H(uops(i).ctrl.srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 174 uops(i).psrc(1) := Mux1H(uops(i).ctrl.srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 175 // int psrc2 should be bypassed from next instruction if it is fused 176 if (i < RenameWidth - 1) { 177 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 178 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 179 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 180 uops(i).psrc(1) := 0.U 181 } 182 } 183 uops(i).psrc(2) := Mux1H(uops(i).ctrl.srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 184 uops(i).psrc(3) := io.vecReadPorts(i)(3) 185 uops(i).old_pdest := Mux1H(Seq( 186 uops(i).ctrl.rfWen -> io.intReadPorts(i).last, 187 uops(i).ctrl.fpWen -> io.fpReadPorts (i).last, 188 uops(i).ctrl.vecWen -> io.vecReadPorts(i).last 189 )) 190 uops(i).eliminatedMove := isMove(i) 191 192 // update pdest 193 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 194 // normal fp inst 195 Mux(needNotIntDest(i), fpFreeList.io.allocatePhyReg(i), 196 /* default */0.U)) 197 198 // Assign performance counters 199 uops(i).debugInfo.renameTime := GTimer() 200 201 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 202 io.out(i).bits := uops(i) 203 // dirty code for fence. The lsrc is passed by imm. 204 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 205 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 206 } 207 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 208 when (io.in(i).bits.ctrl.isSoftPrefetch) { 209 io.out(i).bits.ctrl.fuType := FuType.ldu 210 io.out(i).bits.ctrl.fuOpType := Mux(io.in(i).bits.ctrl.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 211 io.out(i).bits.ctrl.selImm := SelImm.IMM_S 212 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.imm(io.in(i).bits.ctrl.imm.getWidth - 1, 5), 0.U(5.W)) 213 } 214 215 // write speculative rename table 216 // we update rat later inside commit code 217 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 218 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 219 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 220 221 if (i < CommitWidth) { 222 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 223 walkPdest(i) := io.robCommits.info(i).pdest 224 } else { 225 walkPdest(i) := io.out(i).bits.pdest 226 } 227 228 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 229 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 230 } 231 232 /** 233 * How to set psrc: 234 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 235 * - default: psrc from RAT 236 * How to set pdest: 237 * - Mux(isMove, psrc, pdest_from_freelist). 238 * 239 * The critical path of rename lies here: 240 * When move elimination is enabled, we need to update the rat with psrc. 241 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 242 * 243 * If we expand these logic for pdest(N): 244 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 245 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 246 * Mux(bypass(N, N - 2), pdest(N - 2), 247 * ... 248 * Mux(bypass(N, 0), pdest(0), 249 * rat_out(N))...)), 250 * freelist_out(N)) 251 */ 252 // a simple functional model for now 253 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 254 val bypassCond = Wire(Vec(5, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 255 for (i <- 1 until RenameWidth) { 256 val vecCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 257 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 258 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 259 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 260 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 261 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 262 val indexMatch = in.bits.ctrl.ldest === t 263 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 264 indexMatch && writeMatch 265 } 266 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 267 } 268 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 269 (z, next) => Mux(next._2, next._1, z) 270 } 271 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 272 (z, next) => Mux(next._2, next._1, z) 273 } 274 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 275 (z, next) => Mux(next._2, next._1, z) 276 } 277 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 278 (z, next) => Mux(next._2, next._1, z) 279 } 280 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).old_pdest) { 281 (z, next) => Mux(next._2, next._1, z) 282 } 283 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 284 285 // For fused-lui-load, load.src(0) is replaced by the imm. 286 val last_is_lui = io.in(i - 1).bits.ctrl.selImm === SelImm.IMM_U && io.in(i - 1).bits.ctrl.srcType(0) =/= SrcType.pc 287 val this_is_load = io.in(i).bits.ctrl.fuType === FuType.ldu 288 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 289 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 290 when (fused_lui_load) { 291 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 292 val lui_imm = io.in(i - 1).bits.ctrl.imm 293 val ld_imm = io.in(i).bits.ctrl.imm 294 io.out(i).bits.ctrl.srcType(0) := SrcType.imm 295 io.out(i).bits.ctrl.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 296 val psrcWidth = uops(i).psrc.head.getWidth 297 val lui_imm_in_imm = uops(i).ctrl.imm.getWidth - Imm_I().len 298 val left_lui_imm = Imm_U().len - lui_imm_in_imm 299 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 300 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 301 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 302 } 303 304 } 305 306 /** 307 * Instructions commit: update freelist and rename table 308 */ 309 for (i <- 0 until CommitWidth) { 310 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 311 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 312 313 // I. RAT Update 314 // When redirect happens (mis-prediction), don't update the rename table 315 io.intRenamePorts(i).wen := intSpecWen(i) 316 io.intRenamePorts(i).addr := uops(i).ctrl.ldest 317 io.intRenamePorts(i).data := io.out(i).bits.pdest 318 319 io.fpRenamePorts(i).wen := fpSpecWen(i) 320 io.fpRenamePorts(i).addr := uops(i).ctrl.ldest 321 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 322 323 io.vecRenamePorts(i).wen := vecSpecWen(i) 324 io.vecRenamePorts(i).addr := uops(i).ctrl.ldest 325 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 326 327 // II. Free List Update 328 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 329 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 330 fpFreeList.io.freeReq(i) := commitValid && needDestRegCommit(int = false, io.robCommits.info(i)) 331 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 332 333 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(int = true, io.robCommits.info(i)) && !io.robCommits.isWalk 334 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 335 } 336 337 when(io.robCommits.isWalk) { 338 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 339 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 340 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 341 } 342 } 343 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 344 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 345 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 346 } 347 } 348 } 349 350 /* 351 Debug and performance counters 352 */ 353 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 354 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 355 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 356 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 357 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 358 p"lsrc(3):${in.bits.ctrl.lsrc(3)} -> psrc(3):${out.bits.psrc(3)} " + 359 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 360 p"old_pdest:${out.bits.old_pdest}\n" 361 ) 362 } 363 364 for ((x,y) <- io.in.zip(io.out)) { 365 printRenameInfo(x, y) 366 } 367 368 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 369 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 370 for (i <- 0 until CommitWidth) { 371 val info = io.robCommits.info(i) 372 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 373 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}" + 374 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 375 } 376 377 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 378 379 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 380 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 381 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 382 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 383 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 384 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 385 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 386 XSPerfAccumulate("recovery_bubbles", PopCount(io.in.map(_.valid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk))) 387 388 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.ctrl.isMove))) 389 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.ctrl.fuType === FuType.ldu && o.bits.ctrl.srcType(0) === SrcType.imm) 390 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 391 392 val renamePerf = Seq( 393 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 394 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 395 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 396 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 397 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 398 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 399 ) 400 val intFlPerf = intFreeList.getPerfEvents 401 val fpFlPerf = fpFreeList.getPerfEvents 402 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 403 generatePerfEvent() 404} 405