1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 26import xiangshan.backend.fu.FuType 27import xiangshan.backend.rename.freelist._ 28import xiangshan.backend.rob.RobPtr 29import xiangshan.backend.rename.freelist._ 30import xiangshan.mem.mdp._ 31import xiangshan.backend.Bundles.{DecodedInst, DynInst} 32 33class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 34 35 // params alias 36 private val numRegSrc = backendParams.numRegSrc 37 private val numVecRegSrc = backendParams.numVecRegSrc 38 private val numVecRatPorts = numVecRegSrc + 1 // +1 dst 39 40 println(s"[Rename] numRegSrc: $numRegSrc") 41 42 val io = IO(new Bundle() { 43 val redirect = Flipped(ValidIO(new Redirect)) 44 val robCommits = Input(new RobCommitIO) 45 // from decode 46 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 47 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 48 // ssit read result 49 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 50 // waittable read result 51 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 52 // to rename table 53 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 54 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 55 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 56 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 58 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 59 // to dispatch1 60 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 61 // debug arch ports 62 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 63 val debug_vconfig_rat = Input(UInt(PhyRegIdxWidth.W)) 64 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 65 val debug_vec_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 66 }) 67 68 // create free list and rat 69 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 70 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 71 val fpFreeList = Module(new StdFreeList(NRPhyRegs - FpLogicRegs - VecLogicRegs)) 72 73 intRefCounter.io.commit <> io.robCommits 74 intRefCounter.io.redirect := io.redirect.valid 75 intRefCounter.io.debug_int_rat <> io.debug_int_rat 76 intFreeList.io.commit <> io.robCommits 77 intFreeList.io.debug_rat <> io.debug_int_rat 78 fpFreeList.io.commit <> io.robCommits 79 fpFreeList.io.debug_rat <> io.debug_fp_rat 80 81 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 82 // fp and vec share `fpFreeList` 83 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 84 case Reg_I => x.rfWen && x.ldest =/= 0.U 85 case Reg_F => x.fpWen 86 case Reg_V => x.vecWen 87 } 88 def needDestRegCommit[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 89 reg_t match { 90 case Reg_I => x.rfWen 91 case Reg_F => x.fpWen 92 case Reg_V => x.vecWen 93 } 94 } 95 def needDestRegWalk[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 96 reg_t match { 97 case Reg_I => x.rfWen && x.ldest =/= 0.U 98 case Reg_F => x.fpWen 99 case Reg_V => x.vecWen 100 } 101 } 102 103 // connect [redirect + walk] ports for __float point__ & __integer__ free list 104 Seq(fpFreeList, intFreeList).foreach { case fl => 105 fl.io.redirect := io.redirect.valid 106 fl.io.walk := io.robCommits.isWalk 107 } 108 // only when both fp and int free list and dispatch1 has enough space can we do allocation 109 // when isWalk, freelist can definitely allocate 110 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 111 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 112 113 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 114 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 115 116 117 // speculatively assign the instruction with an robIdx 118 val validCount = PopCount(io.in.map(in => in.valid && in.bits.lastUop)) // number of instructions waiting to enter rob (from decode) 119 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 120 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 121 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 122 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 123 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 124 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 125 robIdxHead := robIdxHeadNext 126 127 /** 128 * Rename: allocate free physical register and update rename table 129 */ 130 val uops = Wire(Vec(RenameWidth, new DynInst)) 131 uops.foreach( uop => { 132 uop.srcState := DontCare 133 uop.robIdx := DontCare 134 uop.debugInfo := DontCare 135 uop.lqIdx := DontCare 136 uop.sqIdx := DontCare 137 uop.waitForRobIdx := DontCare 138 uop.singleStep := DontCare 139 }) 140 141 require(RenameWidth >= CommitWidth) 142 val needVecDest = Wire(Vec(RenameWidth, Bool())) 143 val needFpDest = Wire(Vec(RenameWidth, Bool())) 144 val needIntDest = Wire(Vec(RenameWidth, Bool())) 145 val hasValid = Cat(io.in.map(_.valid)).orR 146 147 val isMove = io.in.map(_.bits.isMove) 148 149 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 150 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 151 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 152 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 153 154 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 155 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 156 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 157 158 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 159 160 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 161 162 // uop calculation 163 for (i <- 0 until RenameWidth) { 164 for ((name, data) <- uops(i).elements) { 165 if (io.in(i).bits.elements.contains(name)) { 166 data := io.in(i).bits.elements(name) 167 } 168 } 169 170 // update cf according to ssit result 171 uops(i).storeSetHit := io.ssit(i).valid 172 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 173 uops(i).ssid := io.ssit(i).ssid 174 175 // update cf according to waittable result 176 uops(i).loadWaitBit := io.waittable(i) 177 178 uops(i).replayInst := false.B // set by IQ or MemQ 179 // alloc a new phy reg, fp and vec share the `fpFreeList` 180 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 181 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 182 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 183 if (i < CommitWidth) { 184 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_I, io.robCommits.info(i)) 185 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_F, io.robCommits.info(i)) 186 walkNeedVecDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_V, io.robCommits.info(i)) 187 walkIsMove(i) := io.robCommits.info(i).isMove 188 } 189 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedFpDest(i) || walkNeedVecDest(i), needFpDest(i) || needVecDest(i)) 190 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 191 192 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 193 io.in(i).ready := !hasValid || canOut 194 195 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(in => in.valid && in.bits.lastUop)) 196 197 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 198 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 199 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 200 uops(i).psrc(3) := io.vecReadPorts(i)(3) 201 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 202 203 // int psrc2 should be bypassed from next instruction if it is fused 204 if (i < RenameWidth - 1) { 205 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 206 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 207 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 208 uops(i).psrc(1) := 0.U 209 } 210 } 211 uops(i).oldPdest := Mux1H(Seq( 212 uops(i).rfWen -> io.intReadPorts(i).last, 213 uops(i).fpWen -> io.fpReadPorts (i).last, 214 uops(i).vecWen -> io.vecReadPorts(i).last, 215 )) 216 uops(i).eliminatedMove := isMove(i) 217 218 // update pdest 219 uops(i).pdest := MuxCase(0.U, Seq( 220 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 221 (needFpDest(i) || needVecDest(i)) -> fpFreeList.io.allocatePhyReg(i), 222 )) 223 224 // Assign performance counters 225 uops(i).debugInfo.renameTime := GTimer() 226 227 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 228 io.out(i).bits := uops(i) 229 // Todo: move these shit in decode stage 230 // dirty code for fence. The lsrc is passed by imm. 231 when (io.out(i).bits.fuType === FuType.fence.U) { 232 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 233 } 234 235 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 236// when (io.in(i).bits.isSoftPrefetch) { 237// io.out(i).bits.fuType := FuType.ldu.U 238// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 239// io.out(i).bits.selImm := SelImm.IMM_S 240// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 241// } 242 243 // write speculative rename table 244 // we update rat later inside commit code 245 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 246 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 247 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 248 249 if (i < CommitWidth) { 250 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 251 walkPdest(i) := io.robCommits.info(i).pdest 252 } else { 253 walkPdest(i) := io.out(i).bits.pdest 254 } 255 256 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 257 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 258 } 259 260 /** 261 * How to set psrc: 262 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 263 * - default: psrc from RAT 264 * How to set pdest: 265 * - Mux(isMove, psrc, pdest_from_freelist). 266 * 267 * The critical path of rename lies here: 268 * When move elimination is enabled, we need to update the rat with psrc. 269 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 270 * 271 * If we expand these logic for pdest(N): 272 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 273 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 274 * Mux(bypass(N, N - 2), pdest(N - 2), 275 * ... 276 * Mux(bypass(N, 0), pdest(0), 277 * rat_out(N))...)), 278 * freelist_out(N)) 279 */ 280 // a simple functional model for now 281 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 282 283 // psrc(n) + pdest(1) 284 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 285 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 286 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 287 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 288 for (i <- 1 until RenameWidth) { 289 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 290 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 291 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 292 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 293 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 294 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 295 val indexMatch = in.bits.ldest === t 296 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 297 indexMatch && writeMatch 298 } 299 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 300 } 301 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 302 (z, next) => Mux(next._2, next._1, z) 303 } 304 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 305 (z, next) => Mux(next._2, next._1, z) 306 } 307 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 308 (z, next) => Mux(next._2, next._1, z) 309 } 310 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 311 (z, next) => Mux(next._2, next._1, z) 312 } 313 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 314 (z, next) => Mux(next._2, next._1, z) 315 } 316 io.out(i).bits.oldPdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(pdestLoc)(i-1).asBools).foldLeft(uops(i).oldPdest) { 317 (z, next) => Mux(next._2, next._1, z) 318 } 319 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 320 321 // Todo: better implementation for fields reuse 322 // For fused-lui-load, load.src(0) is replaced by the imm. 323 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 324 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 325 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 326 val fused_lui_load = last_is_lui && this_is_load && lui_to_load && false.B // Todo: enable it 327 when (fused_lui_load) { 328 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 329 val lui_imm = io.in(i - 1).bits.imm(19, 0) 330 val ld_imm = io.in(i).bits.imm 331 io.out(i).bits.srcType(0) := SrcType.imm 332 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 333 val psrcWidth = uops(i).psrc.head.getWidth 334 val lui_imm_in_imm = 20/*Todo: uops(i).imm.getWidth*/ - Imm_I().len 335 val left_lui_imm = Imm_U().len - lui_imm_in_imm 336 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 337 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 338 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 339 } 340 341 } 342 343 /** 344 * Instructions commit: update freelist and rename table 345 */ 346 for (i <- 0 until CommitWidth) { 347 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 348 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 349 350 // I. RAT Update 351 // When redirect happens (mis-prediction), don't update the rename table 352 io.intRenamePorts(i).wen := intSpecWen(i) 353 io.intRenamePorts(i).addr := uops(i).ldest 354 io.intRenamePorts(i).data := io.out(i).bits.pdest 355 356 io.fpRenamePorts(i).wen := fpSpecWen(i) 357 io.fpRenamePorts(i).addr := uops(i).ldest 358 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 359 360 io.vecRenamePorts(i).wen := vecSpecWen(i) 361 io.vecRenamePorts(i).addr := uops(i).ldest 362 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 363 364 // II. Free List Update 365 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 366 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 367 fpFreeList.io.freeReq(i) := commitValid && (needDestRegCommit(Reg_F, io.robCommits.info(i)) || needDestRegCommit(Reg_V, io.robCommits.info(i))) 368 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 369 370 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(Reg_I, io.robCommits.info(i)) && !io.robCommits.isWalk 371 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 372 } 373 374 when(io.robCommits.isWalk) { 375 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 376 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 377 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 378 } 379 } 380 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 381 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 382 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 383 } 384 } 385 } 386 387 /* 388 Debug and performance counters 389 */ 390 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 391 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 392 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 393 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 394 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 395 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest} " + 396 p"old_pdest:${out.bits.oldPdest}\n" 397 // Todo: add no lsrc -> psrc map print 398 ) 399 } 400 401 for ((x,y) <- io.in.zip(io.out)) { 402 printRenameInfo(x, y) 403 } 404 405 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 406 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 407 for (i <- 0 until CommitWidth) { 408 val info = io.robCommits.info(i) 409 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 410 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}" + 411 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 412 } 413 414 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 415 416 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 417 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 418 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 419 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 420 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 421 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 422 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 423 XSPerfAccumulate("recovery_bubbles", PopCount(io.in.map(_.valid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk))) 424 425 XSPerfHistogram("slots_fire", PopCount(io.out.map(_.fire)), true.B, 0, RenameWidth+1, 1) 426 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 427 XSPerfHistogram("slots_valid_pure", PopCount(io.in.map(_.valid)), io.out(0).fire, 0, RenameWidth+1, 1) 428 XSPerfHistogram("slots_valid_rough", PopCount(io.in.map(_.valid)), true.B, 0, RenameWidth+1, 1) 429 430 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 431 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 432 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 433 434 435 val renamePerf = Seq( 436 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 437 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 438 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 439 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 440 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 441 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 442 ) 443 val intFlPerf = intFreeList.getPerfEvents 444 val fpFlPerf = fpFreeList.getPerfEvents 445 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 446 generatePerfEvent() 447} 448