xref: /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala (revision 89fbc90578d54f8bc606cdf7980a7b0cfe63d875) 
1package xiangshan.backend.rename
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils.XSInfo
7
8class RenameBypassInfo extends XSBundle {
9  val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))
10  val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))
11  val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))
12  val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))
13}
14
15class Rename extends XSModule {
16  val io = IO(new Bundle() {
17    val redirect = Flipped(ValidIO(new Redirect))
18    val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
19    // from decode buffer
20    val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl)))
21    // to dispatch1
22    val out = Vec(RenameWidth, DecoupledIO(new MicroOp))
23    val renameBypass = Output(new RenameBypassInfo)
24  })
25
26  def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = {
27    XSInfo(
28      in.valid && in.ready,
29      p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " +
30        p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " +
31        p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " +
32        p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " +
33        p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " +
34        p"old_pdest:${out.bits.old_pdest} " +
35        p"out v:${out.valid} r:${out.ready}\n"
36    )
37  }
38
39  for((x,y) <- io.in.zip(io.out)){
40    printRenameInfo(x, y)
41  }
42
43  val fpFreeList, intFreeList = Module(new FreeList).io
44  val fpRat = Module(new RenameTable(float = true)).io
45  val intRat = Module(new RenameTable(float = false)).io
46
47  fpFreeList.redirect := io.redirect
48  intFreeList.redirect := io.redirect
49
50  val flush = io.redirect.valid && (io.redirect.bits.isException || io.redirect.bits.isFlushPipe) // TODO: need check by JiaWei
51  fpRat.flush := flush
52  intRat.flush := flush
53
54  def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = {
55    {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)}
56  }
57  fpFreeList.walk.valid := io.roqCommits(0).valid && io.roqCommits(0).bits.isWalk
58  intFreeList.walk.valid := io.roqCommits(0).valid && io.roqCommits(0).bits.isWalk
59  fpFreeList.walk.bits := PopCount(io.roqCommits.map(c => c.valid && needDestReg(true, c.bits.uop)))
60  intFreeList.walk.bits := PopCount(io.roqCommits.map(c => c.valid && needDestReg(false, c.bits.uop)))
61
62  val uops = Wire(Vec(RenameWidth, new MicroOp))
63
64  uops.foreach( uop => {
65//    uop.brMask := DontCare
66//    uop.brTag := DontCare
67    uop.src1State := DontCare
68    uop.src2State := DontCare
69    uop.src3State := DontCare
70    uop.roqIdx := DontCare
71    uop.diffTestDebugLrScValid := DontCare
72    uop.lqIdx := DontCare
73    uop.sqIdx := DontCare
74  })
75
76  val needFpDest = Wire(Vec(RenameWidth, Bool()))
77  val needIntDest = Wire(Vec(RenameWidth, Bool()))
78  var lastReady = WireInit(io.out(0).ready)
79  // debug assert
80  val outRdy = Cat(io.out.map(_.ready))
81  assert(outRdy===0.U || outRdy.andR())
82  for(i <- 0 until RenameWidth) {
83    uops(i).cf := io.in(i).bits.cf
84    uops(i).ctrl := io.in(i).bits.ctrl
85    uops(i).brTag := io.in(i).bits.brTag
86
87    val inValid = io.in(i).valid
88
89    // alloc a new phy reg
90    needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits)
91    needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits)
92    fpFreeList.allocReqs(i) := needFpDest(i) && lastReady
93    intFreeList.allocReqs(i) := needIntDest(i) && lastReady
94    val fpCanAlloc = fpFreeList.canAlloc(i)
95    val intCanAlloc = intFreeList.canAlloc(i)
96    val this_can_alloc = Mux(
97      needIntDest(i),
98      intCanAlloc,
99      Mux(
100        needFpDest(i),
101        fpCanAlloc,
102        true.B
103      )
104    )
105    io.in(i).ready := lastReady && this_can_alloc
106
107    // do checkpoints when a branch inst come
108    for(fl <- Seq(fpFreeList, intFreeList)){
109      fl.cpReqs(i).valid := inValid
110      fl.cpReqs(i).bits := io.in(i).bits.brTag
111    }
112
113    lastReady = io.in(i).ready
114
115    uops(i).pdest := Mux(needIntDest(i),
116      intFreeList.pdests(i),
117      Mux(
118        uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen,
119        0.U, fpFreeList.pdests(i)
120      )
121    )
122
123    io.out(i).valid := io.in(i).fire()
124    io.out(i).bits := uops(i)
125
126    // write rename table
127    def writeRat(fp: Boolean) = {
128      val rat = if(fp) fpRat else intRat
129      val freeList = if(fp) fpFreeList else intFreeList
130      // speculative inst write
131      val specWen = freeList.allocReqs(i) && freeList.canAlloc(i)
132      // walk back write
133      val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop)
134      val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk
135
136      rat.specWritePorts(i).wen := specWen || walkWen
137      rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest)
138      rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest)
139
140      XSInfo(walkWen,
141        {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" +
142          p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
143      )
144
145      rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk
146      rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest
147      rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest
148
149      XSInfo(rat.archWritePorts(i).wen,
150        {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" +
151          p" pdest:${rat.archWritePorts(i).wdata}\n"
152      )
153
154      freeList.deallocReqs(i) := rat.archWritePorts(i).wen
155      freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest
156
157    }
158
159    writeRat(fp = false)
160    writeRat(fp = true)
161
162    // read rename table
163    def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = {
164      val rat = if(fp) fpRat else intRat
165      val srcCnt = lsrcList.size
166      val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W)))
167      val old_pdest = Wire(UInt(PhyRegIdxWidth.W))
168      for(k <- 0 until srcCnt+1){
169        val rportIdx = i * (srcCnt+1) + k
170        if(k != srcCnt){
171          rat.readPorts(rportIdx).addr := lsrcList(k)
172          psrcVec(k) := rat.readPorts(rportIdx).rdata
173        } else {
174          rat.readPorts(rportIdx).addr := ldest
175          old_pdest := rat.readPorts(rportIdx).rdata
176        }
177      }
178      (psrcVec, old_pdest)
179    }
180    val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3)
181    val ldest = uops(i).ctrl.ldest
182    val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false)
183    val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true)
184    uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0))
185    uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1))
186    uops(i).psrc3 := fpPhySrcVec(2)
187    uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest)
188  }
189
190  // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage.
191  // Instead, we determine whether there're some dependences between the valid instructions.
192  for (i <- 1 until RenameWidth) {
193    io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => {
194      val fpMatch  = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp
195      val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg
196      (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1
197    }).reverse)
198    io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => {
199      val fpMatch  = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp
200      val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg
201      (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2
202    }).reverse)
203    io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => {
204      val fpMatch  = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp
205      val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg
206      (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3
207    }).reverse)
208    io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => {
209      val fpMatch  = needFpDest(j) && needFpDest(i)
210      val intMatch = needIntDest(j) && needIntDest(i)
211      (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest
212    }).reverse)
213  }
214}
215