1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31import xiangshan.ExceptionNO._ 32import xiangshan.backend.fu.FuType._ 33import xiangshan.mem.{EewLog2, GenUSWholeEmul} 34import xiangshan.mem.GenRealFlowNum 35import xiangshan.backend.trace._ 36 37class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 38 39 // params alias 40 private val numRegSrc = backendParams.numRegSrc 41 private val numVecRegSrc = backendParams.numVecRegSrc 42 private val numVecRatPorts = numVecRegSrc 43 44 println(s"[Rename] numRegSrc: $numRegSrc") 45 46 val io = IO(new Bundle() { 47 val redirect = Flipped(ValidIO(new Redirect)) 48 val rabCommits = Input(new RabCommitIO) 49 // from csr 50 val singleStep = Input(Bool()) 51 // from decode 52 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 53 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 54 // ssit read result 55 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 56 // waittable read result 57 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 58 // to rename table 59 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 60 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 61 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 62 val v0ReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 63 val vlReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 64 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(IntLogicRegs)))) 65 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(FpLogicRegs)))) 66 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(VecLogicRegs)))) 67 val v0RenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(V0LogicRegs)))) 68 val vlRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(VlLogicRegs)))) 69 // from rename table 70 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 71 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 72 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 73 val v0_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 74 val vl_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 75 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 76 // to dispatch1 77 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 78 // for snapshots 79 val snpt = Input(new SnapshotPort) 80 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 81 val snptIsFull= Input(Bool()) 82 // debug arch ports 83 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 84 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 85 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Input(UInt(PhyRegIdxWidth.W)))) else None 86 val debug_v0_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 87 val debug_vl_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 88 // perf only 89 val stallReason = new Bundle { 90 val in = Flipped(new StallReasonIO(RenameWidth)) 91 val out = new StallReasonIO(RenameWidth) 92 } 93 }) 94 95 // io alias 96 private val dispatchCanAcc = io.out.head.ready 97 98 val compressUnit = Module(new CompressUnit()) 99 // create free list and rat 100 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 101 val fpFreeList = Module(new StdFreeList(FpPhyRegs - FpLogicRegs, FpLogicRegs, Reg_F)) 102 val vecFreeList = Module(new StdFreeList(VfPhyRegs - VecLogicRegs, VecLogicRegs, Reg_V, 31)) 103 val v0FreeList = Module(new StdFreeList(V0PhyRegs - V0LogicRegs, V0LogicRegs, Reg_V0, 1)) 104 val vlFreeList = Module(new StdFreeList(VlPhyRegs - VlLogicRegs, VlLogicRegs, Reg_Vl, 1)) 105 106 107 intFreeList.io.commit <> io.rabCommits 108 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 109 fpFreeList.io.commit <> io.rabCommits 110 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 111 vecFreeList.io.commit <> io.rabCommits 112 vecFreeList.io.debug_rat.foreach(_ <> io.debug_vec_rat.get) 113 v0FreeList.io.commit <> io.rabCommits 114 v0FreeList.io.debug_rat.foreach(_ <> io.debug_v0_rat.get) 115 vlFreeList.io.commit <> io.rabCommits 116 vlFreeList.io.debug_rat.foreach(_ <> io.debug_vl_rat.get) 117 118 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 119 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 120 case Reg_I => x.rfWen && x.ldest =/= 0.U 121 case Reg_F => x.fpWen 122 case Reg_V => x.vecWen 123 case Reg_V0 => x.v0Wen 124 case Reg_Vl => x.vlWen 125 } 126 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 127 reg_t match { 128 case Reg_I => x.rfWen 129 case Reg_F => x.fpWen 130 case Reg_V => x.vecWen 131 case Reg_V0 => x.v0Wen 132 case Reg_Vl => x.vlWen 133 } 134 } 135 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 136 reg_t match { 137 case Reg_I => x.rfWen && x.ldest =/= 0.U 138 case Reg_F => x.fpWen 139 case Reg_V => x.vecWen 140 case Reg_V0 => x.v0Wen 141 case Reg_Vl => x.vlWen 142 } 143 } 144 145 // connect [redirect + walk] ports for fp & vec & int free list 146 Seq(fpFreeList, vecFreeList, intFreeList, v0FreeList, vlFreeList).foreach { case fl => 147 fl.io.redirect := io.redirect.valid 148 fl.io.walk := io.rabCommits.isWalk 149 } 150 // only when all free list and dispatch1 has enough space can we do allocation 151 // when isWalk, freelist can definitely allocate 152 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 153 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 154 vecFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 155 v0FreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 156 vlFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 157 158 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ vec free list ready ++ not walk 159 val canOut = dispatchCanAcc && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 160 161 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 162 sink.valid := source.valid && !io.singleStep 163 sink.bits := source.bits 164 } 165 val needRobFlags = compressUnit.io.out.needRobFlags 166 val instrSizesVec = compressUnit.io.out.instrSizes 167 val compressMasksVec = compressUnit.io.out.masks 168 169 // speculatively assign the instruction with an robIdx 170 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 171 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 172 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 173 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 174 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 175 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 176 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 177 robIdxHead := robIdxHeadNext 178 179 /** 180 * Rename: allocate free physical register and update rename table 181 */ 182 val uops = Wire(Vec(RenameWidth, new DynInst)) 183 uops.foreach( uop => { 184 uop.srcState := DontCare 185 uop.debugInfo := DontCare 186 uop.lqIdx := DontCare 187 uop.sqIdx := DontCare 188 uop.waitForRobIdx := DontCare 189 uop.singleStep := DontCare 190 uop.snapshot := DontCare 191 uop.srcLoadDependency := DontCare 192 uop.numLsElem := DontCare 193 uop.hasException := DontCare 194 uop.useRegCache := DontCare 195 uop.regCacheIdx := DontCare 196 uop.traceBlockInPipe := DontCare 197 }) 198 private val fuType = uops.map(_.fuType) 199 private val fuOpType = uops.map(_.fuOpType) 200 private val vtype = uops.map(_.vpu.vtype) 201 private val sew = vtype.map(_.vsew) 202 private val lmul = vtype.map(_.vlmul) 203 private val eew = uops.map(_.vpu.veew) 204 private val mop = fuOpType.map(fuOpTypeItem => LSUOpType.getVecLSMop(fuOpTypeItem)) 205 private val isVlsType = fuType.map(fuTypeItem => isVls(fuTypeItem)) 206 private val isSegment = fuType.map(fuTypeItem => isVsegls(fuTypeItem)) 207 private val isUnitStride = fuOpType.map(fuOpTypeItem => LSUOpType.isAllUS(fuOpTypeItem)) 208 private val nf = fuOpType.zip(uops.map(_.vpu.nf)).map { case (fuOpTypeItem, nfItem) => Mux(LSUOpType.isWhole(fuOpTypeItem), 0.U, nfItem) } 209 private val mulBits = 3 // dirty code 210 private val emul = fuOpType.zipWithIndex.map { case (fuOpTypeItem, index) => 211 Mux( 212 LSUOpType.isWhole(fuOpTypeItem), 213 GenUSWholeEmul(nf(index)), 214 Mux( 215 LSUOpType.isMasked(fuOpTypeItem), 216 0.U(mulBits.W), 217 EewLog2(eew(index)) - sew(index) + lmul(index) 218 ) 219 ) 220 } 221 private val isVecUnitType = isVlsType.zip(isUnitStride).map { case (isVlsTypeItme, isUnitStrideItem) => 222 isVlsTypeItme && isUnitStrideItem 223 } 224 private val instType = isSegment.zip(mop).map { case (isSegementItem, mopItem) => Cat(isSegementItem, mopItem) } 225 // There is no way to calculate the 'flow' for 'unit-stride' exactly: 226 // Whether 'unit-stride' needs to be split can only be known after obtaining the address. 227 // For scalar instructions, this is not handled here, and different assignments are done later according to the situation. 228 private val numLsElem = instType.zipWithIndex.map { case (instTypeItem, index) => 229 Mux( 230 isVecUnitType(index), 231 VecMemUnitStrideMaxFlowNum.U, 232 GenRealFlowNum(instTypeItem, emul(index), lmul(index), eew(index), sew(index)) 233 ) 234 } 235 uops.zipWithIndex.map { case(u, i) => 236 u.numLsElem := Mux(io.in(i).valid & isVlsType(i), numLsElem(i), 0.U) 237 } 238 239 val needVecDest = Wire(Vec(RenameWidth, Bool())) 240 val needFpDest = Wire(Vec(RenameWidth, Bool())) 241 val needIntDest = Wire(Vec(RenameWidth, Bool())) 242 val needV0Dest = Wire(Vec(RenameWidth, Bool())) 243 val needVlDest = Wire(Vec(RenameWidth, Bool())) 244 private val inHeadValid = io.in.head.valid 245 246 val isMove = Wire(Vec(RenameWidth, Bool())) 247 isMove zip io.in.map(_.bits) foreach { 248 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 249 } 250 251 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 252 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 253 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 254 val walkNeedV0Dest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 255 val walkNeedVlDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 256 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 257 258 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 259 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 260 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 261 val v0SpecWen = Wire(Vec(RenameWidth, Bool())) 262 val vlSpecWen = Wire(Vec(RenameWidth, Bool())) 263 264 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 265 266 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 267 268 // uop calculation 269 for (i <- 0 until RenameWidth) { 270 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 271 272 // update cf according to ssit result 273 uops(i).storeSetHit := io.ssit(i).valid 274 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 275 uops(i).ssid := io.ssit(i).ssid 276 277 // update cf according to waittable result 278 uops(i).loadWaitBit := io.waittable(i) 279 280 uops(i).replayInst := false.B // set by IQ or MemQ 281 // alloc a new phy reg 282 needV0Dest(i) := io.in(i).valid && needDestReg(Reg_V0, io.in(i).bits) 283 needVlDest(i) := io.in(i).valid && needDestReg(Reg_Vl, io.in(i).bits) 284 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 285 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 286 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 287 if (i < RabCommitWidth) { 288 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 289 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 290 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 291 walkNeedV0Dest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V0, io.rabCommits.info(i)) 292 walkNeedVlDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_Vl, io.rabCommits.info(i)) 293 walkIsMove(i) := io.rabCommits.info(i).isMove 294 } 295 fpFreeList.io.allocateReq(i) := needFpDest(i) 296 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) 297 vecFreeList.io.allocateReq(i) := needVecDest(i) 298 vecFreeList.io.walkReq(i) := walkNeedVecDest(i) 299 v0FreeList.io.allocateReq(i) := needV0Dest(i) 300 v0FreeList.io.walkReq(i) := walkNeedV0Dest(i) 301 vlFreeList.io.allocateReq(i) := needVlDest(i) 302 vlFreeList.io.walkReq(i) := walkNeedVlDest(i) 303 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 304 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 305 306 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 307 io.in(i).ready := !io.in(0).valid || canOut 308 309 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 310 uops(i).instrSize := instrSizesVec(i) 311 val hasExceptionExceptFlushPipe = Cat(selectFrontend(uops(i).exceptionVec) :+ uops(i).exceptionVec(illegalInstr) :+ uops(i).exceptionVec(virtualInstr)).orR || TriggerAction.isDmode(uops(i).trigger) 312 when(isMove(i) || hasExceptionExceptFlushPipe) { 313 uops(i).numUops := 0.U 314 uops(i).numWB := 0.U 315 } 316 if (i > 0) { 317 when(!needRobFlags(i - 1)) { 318 uops(i).firstUop := false.B 319 uops(i).ftqPtr := uops(i - 1).ftqPtr 320 uops(i).ftqOffset := uops(i - 1).ftqOffset 321 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 322 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 323 } 324 } 325 when(!needRobFlags(i)) { 326 uops(i).lastUop := false.B 327 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 328 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 329 } 330 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 331 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 332 // vector instructions' uopSplitType cannot be UopSplitType.SCA_SIM 333 uops(i).dirtyVs := (compressMasksVec(i) & Cat(io.in.map(_.bits.uopSplitType =/= UopSplitType.SCA_SIM).reverse)).orR 334 // psrc0,psrc1,psrc2 don't require v0ReadPorts because their srcType can distinguish whether they are V0 or not 335 uops(i).psrc(0) := Mux1H(uops(i).srcType(0)(2, 0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 336 uops(i).psrc(1) := Mux1H(uops(i).srcType(1)(2, 0), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 337 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 338 uops(i).psrc(3) := io.v0ReadPorts(i)(0) 339 uops(i).psrc(4) := io.vlReadPorts(i)(0) 340 341 // int psrc2 should be bypassed from next instruction if it is fused 342 if (i < RenameWidth - 1) { 343 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 344 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 345 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 346 uops(i).psrc(1) := 0.U 347 } 348 } 349 uops(i).eliminatedMove := isMove(i) 350 351 // update pdest 352 uops(i).pdest := MuxCase(0.U, Seq( 353 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 354 needFpDest(i) -> fpFreeList.io.allocatePhyReg(i), 355 needVecDest(i) -> vecFreeList.io.allocatePhyReg(i), 356 needV0Dest(i) -> v0FreeList.io.allocatePhyReg(i), 357 needVlDest(i) -> vlFreeList.io.allocatePhyReg(i), 358 )) 359 360 // Assign performance counters 361 uops(i).debugInfo.renameTime := GTimer() 362 363 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 364 io.out(i).bits := uops(i) 365 // Todo: move these shit in decode stage 366 // dirty code for fence. The lsrc is passed by imm. 367 when (io.out(i).bits.fuType === FuType.fence.U) { 368 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 369 } 370 371 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 372// when (io.in(i).bits.isSoftPrefetch) { 373// io.out(i).bits.fuType := FuType.ldu.U 374// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 375// io.out(i).bits.selImm := SelImm.IMM_S 376// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 377// } 378 379 // dirty code for lui+addi(w) fusion 380 if (i < RenameWidth - 1) { 381 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 382 when (fused_lui32) { 383 val lui_imm = io.in(i).bits.imm(19, 0) 384 val add_imm = io.in(i + 1).bits.imm(11, 0) 385 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 386 io.out(i).bits.imm := Cat(lui_imm, add_imm) 387 } 388 } 389 390 // write speculative rename table 391 // we update rat later inside commit code 392 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 393 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 394 vecSpecWen(i) := needVecDest(i) && vecFreeList.io.canAllocate && vecFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 395 v0SpecWen(i) := needV0Dest(i) && v0FreeList.io.canAllocate && v0FreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 396 vlSpecWen(i) := needVlDest(i) && vlFreeList.io.canAllocate && vlFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 397 398 399 if (i < RabCommitWidth) { 400 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 401 walkPdest(i) := io.rabCommits.info(i).pdest 402 } else { 403 walkPdest(i) := io.out(i).bits.pdest 404 } 405 } 406 407 /** 408 * trace begin 409 */ 410 val inVec = io.in.map(_.bits) 411 val canRobCompressVec = inVec.map(_.canRobCompress) 412 val isRVCVec = inVec.map(_.preDecodeInfo.isRVC) 413 val halfWordNumVec = (0 until RenameWidth).map{ 414 i => compressMasksVec(i).asBools.zip(isRVCVec).map{ 415 case (mask, isRVC) => Mux(mask, Mux(isRVC, 1.U, 2.U), 0.U) 416 } 417 } 418 419 for (i <- 0 until RenameWidth) { 420 // iretire 421 uops(i).traceBlockInPipe.iretire := Mux(canRobCompressVec(i), 422 halfWordNumVec(i).reduce(_ +& _), 423 Mux(isRVCVec(i), 1.U, 2.U) 424 ) 425 426 // ilastsize 427 val j = i 428 val lastIsRVC = WireInit(false.B) 429 (j until RenameWidth).map { j => 430 when(compressMasksVec(i)(j)) { 431 lastIsRVC := io.in(j).bits.preDecodeInfo.isRVC 432 } 433 } 434 435 uops(i).traceBlockInPipe.ilastsize := Mux(canRobCompressVec(i), 436 Mux(lastIsRVC, Ilastsize.HalfWord, Ilastsize.Word), 437 Mux(isRVCVec(i), Ilastsize.HalfWord, Ilastsize.Word) 438 ) 439 440 // itype 441 uops(i).traceBlockInPipe.itype := Itype.jumpTypeGen(inVec(i).preDecodeInfo.brType, inVec(i).ldest.asTypeOf(new OpRegType), inVec(i).lsrc(0).asTypeOf((new OpRegType))) 442 } 443 /** 444 * trace end 445 */ 446 447 /** 448 * How to set psrc: 449 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 450 * - default: psrc from RAT 451 * How to set pdest: 452 * - Mux(isMove, psrc, pdest_from_freelist). 453 * 454 * The critical path of rename lies here: 455 * When move elimination is enabled, we need to update the rat with psrc. 456 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 457 * 458 * If we expand these logic for pdest(N): 459 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 460 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 461 * Mux(bypass(N, N - 2), pdest(N - 2), 462 * ... 463 * Mux(bypass(N, 0), pdest(0), 464 * rat_out(N))...)), 465 * freelist_out(N)) 466 */ 467 // a simple functional model for now 468 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 469 470 // psrc(n) + pdest(1) 471 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 472 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 473 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 474 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 475 for (i <- 1 until RenameWidth) { 476 val v0Cond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 477 if (i == 3) (s === SrcType.vp) || (s === SrcType.v0) 478 else false.B 479 } :+ needV0Dest(i) 480 val vlCond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 481 if (i == 4) s === SrcType.vp 482 else false.B 483 } :+ needVlDest(i) 484 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 485 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 486 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 487 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 488 for ((((((cond1, (condV0, condVl)), cond2), cond3), t), j) <- vecCond.zip(v0Cond.zip(vlCond)).zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 489 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 490 val indexMatch = in.bits.ldest === t 491 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 492 val v0vlMatch = condV0 && needV0Dest(j) || condVl && needVlDest(j) 493 indexMatch && writeMatch || v0vlMatch 494 } 495 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 496 } 497 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 498 (z, next) => Mux(next._2, next._1, z) 499 } 500 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 501 (z, next) => Mux(next._2, next._1, z) 502 } 503 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 504 (z, next) => Mux(next._2, next._1, z) 505 } 506 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 507 (z, next) => Mux(next._2, next._1, z) 508 } 509 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 510 (z, next) => Mux(next._2, next._1, z) 511 } 512 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 513 514 // Todo: better implementation for fields reuse 515 // For fused-lui-load, load.src(0) is replaced by the imm. 516 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 517 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 518 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 519 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 520 when (fused_lui_load) { 521 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 522 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 523 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 524 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 525 io.out(i).bits.srcType(0) := SrcType.imm 526 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 527 } 528 529 } 530 531 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 532 val lastCycleCreateSnpt = RegInit(false.B) 533 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 534 val sameSnptDistance = (RobCommitWidth * 4).U 535 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 536 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 537 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 538 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 539 io.out.map{ x => 540 x.bits.hasException := Cat(selectFrontend(x.bits.exceptionVec) :+ x.bits.exceptionVec(illegalInstr) :+ x.bits.exceptionVec(virtualInstr)).orR || TriggerAction.isDmode(x.bits.trigger) 541 } 542 if(backendParams.debugEn){ 543 dontTouch(robIdxHeadNext) 544 dontTouch(notInSameSnpt) 545 dontTouch(genSnapshot) 546 } 547 intFreeList.io.snpt := io.snpt 548 fpFreeList.io.snpt := io.snpt 549 vecFreeList.io.snpt := io.snpt 550 v0FreeList.io.snpt := io.snpt 551 vlFreeList.io.snpt := io.snpt 552 intFreeList.io.snpt.snptEnq := genSnapshot 553 fpFreeList.io.snpt.snptEnq := genSnapshot 554 vecFreeList.io.snpt.snptEnq := genSnapshot 555 v0FreeList.io.snpt.snptEnq := genSnapshot 556 vlFreeList.io.snpt.snptEnq := genSnapshot 557 558 /** 559 * Instructions commit: update freelist and rename table 560 */ 561 for (i <- 0 until RabCommitWidth) { 562 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 563 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 564 565 // I. RAT Update 566 // When redirect happens (mis-prediction), don't update the rename table 567 io.intRenamePorts(i).wen := intSpecWen(i) 568 io.intRenamePorts(i).addr := uops(i).ldest(log2Ceil(IntLogicRegs) - 1, 0) 569 io.intRenamePorts(i).data := io.out(i).bits.pdest 570 571 io.fpRenamePorts(i).wen := fpSpecWen(i) 572 io.fpRenamePorts(i).addr := uops(i).ldest(log2Ceil(FpLogicRegs) - 1, 0) 573 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 574 575 io.vecRenamePorts(i).wen := vecSpecWen(i) 576 io.vecRenamePorts(i).addr := uops(i).ldest(log2Ceil(VecLogicRegs) - 1, 0) 577 io.vecRenamePorts(i).data := vecFreeList.io.allocatePhyReg(i) 578 579 io.v0RenamePorts(i).wen := v0SpecWen(i) 580 io.v0RenamePorts(i).addr := uops(i).ldest(log2Ceil(V0LogicRegs) - 1, 0) 581 io.v0RenamePorts(i).data := v0FreeList.io.allocatePhyReg(i) 582 583 io.vlRenamePorts(i).wen := vlSpecWen(i) 584 io.vlRenamePorts(i).addr := uops(i).ldest(log2Ceil(VlLogicRegs) - 1, 0) 585 io.vlRenamePorts(i).data := vlFreeList.io.allocatePhyReg(i) 586 587 // II. Free List Update 588 intFreeList.io.freeReq(i) := io.int_need_free(i) 589 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 590 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_F, io.rabCommits.info(i))) 591 fpFreeList.io.freePhyReg(i) := io.fp_old_pdest(i) 592 vecFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V, io.rabCommits.info(i))) 593 vecFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 594 v0FreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V0, io.rabCommits.info(i))) 595 v0FreeList.io.freePhyReg(i) := io.v0_old_pdest(i) 596 vlFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_Vl, io.rabCommits.info(i))) 597 vlFreeList.io.freePhyReg(i) := io.vl_old_pdest(i) 598 } 599 600 /* 601 Debug and performance counters 602 */ 603 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 604 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 605 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 606 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 607 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 608 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 609 ) 610 } 611 612 for ((x,y) <- io.in.zip(io.out)) { 613 printRenameInfo(x, y) 614 } 615 616 io.out.map { case x => 617 when(x.valid && x.bits.rfWen){ 618 assert(x.bits.ldest =/= 0.U, "rfWen cannot be 1 when Int regfile ldest is 0") 619 } 620 } 621 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 622 // bad speculation 623 val recStall = io.redirect.valid || io.rabCommits.isWalk 624 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 625 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 626 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 627 XSPerfAccumulate("recovery_stall", recStall) 628 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 629 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 630 XSPerfAccumulate("other_recovery_stall", otherRecStall) 631 // freelist stall 632 val notRecStall = !io.out.head.valid && !recStall 633 val intFlStall = notRecStall && inHeadValid && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 634 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 635 val vecFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 636 val v0FlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 637 val vlFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 638 val multiFlStall = notRecStall && inHeadValid && (PopCount(Cat( 639 !intFreeList.io.canAllocate, 640 !fpFreeList.io.canAllocate, 641 !vecFreeList.io.canAllocate, 642 !v0FreeList.io.canAllocate, 643 !vlFreeList.io.canAllocate, 644 )) > 1.U) 645 // other stall 646 val otherStall = notRecStall && !intFlStall && !fpFlStall && !vecFlStall && !v0FlStall && !vlFlStall && !multiFlStall 647 648 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 649 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 650 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 651 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 652 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 653 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 654 intFlStall -> TopDownCounters.IntFlStall.id.U, 655 fpFlStall -> TopDownCounters.FpFlStall.id.U, 656 vecFlStall -> TopDownCounters.VecFlStall.id.U, 657 v0FlStall -> TopDownCounters.V0FlStall.id.U, 658 vlFlStall -> TopDownCounters.VlFlStall.id.U, 659 multiFlStall -> TopDownCounters.MultiFlStall.id.U, 660 ) 661 )) 662 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 663 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 664 } 665 666 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 667 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 668 for (i <- 0 until RabCommitWidth) { 669 val info = io.rabCommits.info(i) 670 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 671 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen} v0Wen:${info.v0Wen} vlWen:${info.vlWen}") 672 } 673 674 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 675 676 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 677 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 678 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 679 XSPerfAccumulate("wait_cycle", !io.in.head.valid && dispatchCanAcc) 680 681 // These stall reasons could overlap each other, but we configure the priority as fellows. 682 // walk stall > dispatch stall > int freelist stall > fp freelist stall 683 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 684 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 685 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc 686 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 687 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 688 private val stallForVecFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 689 private val stallForV0FL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 690 private val stallForVlFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 691 XSPerfAccumulate("stall_cycle", inHeadStall) 692 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 693 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 694 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 695 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 696 XSPerfAccumulate("stall_cycle_vec", stallForVecFL) 697 XSPerfAccumulate("stall_cycle_vec", stallForV0FL) 698 XSPerfAccumulate("stall_cycle_vec", stallForVlFL) 699 700 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 701 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 702 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 703 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 704 705 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 706 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 707 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 708 709 val renamePerf = Seq( 710 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 711 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 712 ("rename_stall ", inHeadStall), 713 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 714 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc), 715 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate), 716 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 717 ("rename_stall_cycle_vec ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate), 718 ("rename_stall_cycle_v0 ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate), 719 ("rename_stall_cycle_vl ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate), 720 ) 721 val intFlPerf = intFreeList.getPerfEvents 722 val fpFlPerf = fpFreeList.getPerfEvents 723 val vecFlPerf = vecFreeList.getPerfEvents 724 val v0FlPerf = v0FreeList.getPerfEvents 725 val vlFlPerf = vlFreeList.getPerfEvents 726 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf ++ v0FlPerf ++ vlFlPerf 727 generatePerfEvent() 728} 729