1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.RobPtr 30import xiangshan.mem.mdp._ 31 32class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 33 34 // params alias 35 private val numRegSrc = backendParams.numRegSrc 36 private val numVecRegSrc = backendParams.numVecRegSrc 37 private val numVecRatPorts = numVecRegSrc + 1 // +1 dst 38 39 println(s"[Rename] numRegSrc: $numRegSrc") 40 41 val io = IO(new Bundle() { 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val robCommits = Input(new RobCommitIO) 44 // from decode 45 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 46 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 47 // ssit read result 48 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 49 // waittable read result 50 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 51 // to rename table 52 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 53 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 54 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 55 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 58 // from rename table 59 val int_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 60 val fp_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 61 val vec_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 62 val int_need_free = Vec(CommitWidth, Input(Bool())) 63 // to dispatch1 64 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 65 // for snapshots 66 val snpt = Input(new SnapshotPort) 67 // debug arch ports 68 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 69 val debug_vconfig_rat = if (backendParams.debugEn) Some(Input(UInt(PhyRegIdxWidth.W))) else None 70 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 71 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 72 // perf only 73 val stallReason = new Bundle { 74 val in = Flipped(new StallReasonIO(RenameWidth)) 75 val out = new StallReasonIO(RenameWidth) 76 } 77 }) 78 79 val compressUnit = Module(new CompressUnit()) 80 // create free list and rat 81 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 82 val fpFreeList = Module(new StdFreeList(VfPhyRegs - FpLogicRegs - VecLogicRegs)) 83 84 intFreeList.io.commit <> io.robCommits 85 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 86 fpFreeList.io.commit <> io.robCommits 87 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 88 89 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 90 // fp and vec share `fpFreeList` 91 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 92 case Reg_I => x.rfWen && x.ldest =/= 0.U 93 case Reg_F => x.fpWen 94 case Reg_V => x.vecWen 95 } 96 def needDestRegCommit[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 97 reg_t match { 98 case Reg_I => x.rfWen 99 case Reg_F => x.fpWen 100 case Reg_V => x.vecWen 101 } 102 } 103 def needDestRegWalk[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 104 reg_t match { 105 case Reg_I => x.rfWen && x.ldest =/= 0.U 106 case Reg_F => x.fpWen 107 case Reg_V => x.vecWen 108 } 109 } 110 111 // connect [redirect + walk] ports for __float point__ & __integer__ free list 112 Seq(fpFreeList, intFreeList).foreach { case fl => 113 fl.io.redirect := io.redirect.valid 114 fl.io.walk := io.robCommits.isWalk 115 } 116 // only when both fp and int free list and dispatch1 has enough space can we do allocation 117 // when isWalk, freelist can definitely allocate 118 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 119 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 120 121 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 122 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 123 124 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 125 sink.valid := source.valid 126 sink.bits := source.bits 127 } 128 val needRobFlags = compressUnit.io.out.needRobFlags 129 val instrSizesVec = compressUnit.io.out.instrSizes 130 val compressMasksVec = compressUnit.io.out.masks 131 132 // speculatively assign the instruction with an robIdx 133 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 134 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 135 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 136 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 137 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 138 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 139 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 140 robIdxHead := robIdxHeadNext 141 142 /** 143 * Rename: allocate free physical register and update rename table 144 */ 145 val uops = Wire(Vec(RenameWidth, new DynInst)) 146 uops.foreach( uop => { 147 uop.srcState := DontCare 148 uop.debugInfo := DontCare 149 uop.lqIdx := DontCare 150 uop.sqIdx := DontCare 151 uop.waitForRobIdx := DontCare 152 uop.singleStep := DontCare 153 uop.snapshot := DontCare 154 uop.dataSource := DontCare 155 uop.l1ExuOH := DontCare 156 }) 157 158 require(RenameWidth >= CommitWidth) 159 val needVecDest = Wire(Vec(RenameWidth, Bool())) 160 val needFpDest = Wire(Vec(RenameWidth, Bool())) 161 val needIntDest = Wire(Vec(RenameWidth, Bool())) 162 val hasValid = Cat(io.in.map(_.valid)).orR 163 private val inHeadValid = io.in.head.valid 164 165 val isMove = Wire(Vec(RenameWidth, Bool())) 166 isMove zip io.in.map(_.bits) foreach { 167 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 168 } 169 170 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 171 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 172 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 173 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 174 175 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 176 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 177 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 178 179 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 180 181 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 182 183 // uop calculation 184 for (i <- 0 until RenameWidth) { 185 for ((name, data) <- uops(i).elements) { 186 if (io.in(i).bits.elements.contains(name)) { 187 data := io.in(i).bits.elements(name) 188 } 189 } 190 191 // update cf according to ssit result 192 uops(i).storeSetHit := io.ssit(i).valid 193 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 194 uops(i).ssid := io.ssit(i).ssid 195 196 // update cf according to waittable result 197 uops(i).loadWaitBit := io.waittable(i) 198 199 uops(i).replayInst := false.B // set by IQ or MemQ 200 // alloc a new phy reg, fp and vec share the `fpFreeList` 201 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 202 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 203 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 204 if (i < CommitWidth) { 205 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_I, io.robCommits.info(i)) 206 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_F, io.robCommits.info(i)) 207 walkNeedVecDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_V, io.robCommits.info(i)) 208 walkIsMove(i) := io.robCommits.info(i).isMove 209 } 210 fpFreeList.io.allocateReq(i) := needFpDest(i) || needVecDest(i) 211 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) || walkNeedVecDest(i) 212 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 213 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 214 215 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 216 io.in(i).ready := !hasValid || canOut 217 218 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 219 uops(i).instrSize := instrSizesVec(i) 220 when(isMove(i)) { 221 uops(i).numUops := 0.U 222 } 223 if (i > 0) { 224 when(!needRobFlags(i - 1)) { 225 uops(i).firstUop := false.B 226 uops(i).ftqPtr := uops(i - 1).ftqPtr 227 uops(i).ftqOffset := uops(i - 1).ftqOffset 228 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 229 } 230 } 231 when(!needRobFlags(i)) { 232 uops(i).lastUop := false.B 233 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 234 } 235 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 236 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 237 238 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 239 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 240 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 241 uops(i).psrc(3) := io.vecReadPorts(i)(3) 242 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 243 244 // int psrc2 should be bypassed from next instruction if it is fused 245 if (i < RenameWidth - 1) { 246 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 247 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 248 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 249 uops(i).psrc(1) := 0.U 250 } 251 } 252 uops(i).eliminatedMove := isMove(i) 253 254 // update pdest 255 uops(i).pdest := MuxCase(0.U, Seq( 256 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 257 (needFpDest(i) || needVecDest(i)) -> fpFreeList.io.allocatePhyReg(i), 258 )) 259 260 // Assign performance counters 261 uops(i).debugInfo.renameTime := GTimer() 262 263 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 264 io.out(i).bits := uops(i) 265 // Todo: move these shit in decode stage 266 // dirty code for fence. The lsrc is passed by imm. 267 when (io.out(i).bits.fuType === FuType.fence.U) { 268 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 269 } 270 271 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 272// when (io.in(i).bits.isSoftPrefetch) { 273// io.out(i).bits.fuType := FuType.ldu.U 274// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 275// io.out(i).bits.selImm := SelImm.IMM_S 276// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 277// } 278 279 // dirty code for lui+addi(w) fusion 280 if (i < RenameWidth - 1) { 281 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 282 when (fused_lui32) { 283 val lui_imm = io.in(i).bits.imm(19, 0) 284 val add_imm = io.in(i + 1).bits.imm(11, 0) 285 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, add_imm) 286 val lsrcWidth = uops(i).lsrc.head.getWidth 287 val lui_imm_in_imm = ImmUnion.maxLen - Imm_I().len 288 val left_lui_imm = Imm_U().len - lui_imm_in_imm 289 require(2 * lsrcWidth >= left_lui_imm, "cannot fused lui and addi(w) with lsrc") 290 io.out(i).bits.lsrc(0) := lui_imm(lui_imm_in_imm + lsrcWidth - 1, lui_imm_in_imm) 291 io.out(i).bits.lsrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + lsrcWidth) 292 } 293 } 294 295 // write speculative rename table 296 // we update rat later inside commit code 297 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 298 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 299 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 300 301 if (i < CommitWidth) { 302 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 303 walkPdest(i) := io.robCommits.info(i).pdest 304 } else { 305 walkPdest(i) := io.out(i).bits.pdest 306 } 307 } 308 309 /** 310 * How to set psrc: 311 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 312 * - default: psrc from RAT 313 * How to set pdest: 314 * - Mux(isMove, psrc, pdest_from_freelist). 315 * 316 * The critical path of rename lies here: 317 * When move elimination is enabled, we need to update the rat with psrc. 318 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 319 * 320 * If we expand these logic for pdest(N): 321 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 322 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 323 * Mux(bypass(N, N - 2), pdest(N - 2), 324 * ... 325 * Mux(bypass(N, 0), pdest(0), 326 * rat_out(N))...)), 327 * freelist_out(N)) 328 */ 329 // a simple functional model for now 330 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 331 332 // psrc(n) + pdest(1) 333 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 334 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 335 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 336 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 337 for (i <- 1 until RenameWidth) { 338 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 339 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 340 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 341 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 342 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 343 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 344 val indexMatch = in.bits.ldest === t 345 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 346 indexMatch && writeMatch 347 } 348 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 349 } 350 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 351 (z, next) => Mux(next._2, next._1, z) 352 } 353 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 354 (z, next) => Mux(next._2, next._1, z) 355 } 356 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 357 (z, next) => Mux(next._2, next._1, z) 358 } 359 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 360 (z, next) => Mux(next._2, next._1, z) 361 } 362 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 363 (z, next) => Mux(next._2, next._1, z) 364 } 365 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 366 367 // Todo: better implementation for fields reuse 368 // For fused-lui-load, load.src(0) is replaced by the imm. 369 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 370 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 371 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 372 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 373 when (fused_lui_load) { 374 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 375 val lui_imm = io.in(i - 1).bits.imm(19, 0) 376 val ld_imm = io.in(i).bits.imm 377 io.out(i).bits.srcType(0) := SrcType.imm 378 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 379 val psrcWidth = uops(i).psrc.head.getWidth 380 val lui_imm_in_imm = 20/*Todo: uops(i).imm.getWidth*/ - Imm_I().len 381 val left_lui_imm = Imm_U().len - lui_imm_in_imm 382 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 383 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 384 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 385 } 386 387 } 388 389 val hasCFI = VecInit(io.in.map(in => (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire)).asUInt.orR 390 val snapshotCtr = RegInit((4 * CommitWidth).U) 391 val allowSnpt = if (EnableRenameSnapshot) !snapshotCtr.orR else false.B 392 io.out.head.bits.snapshot := hasCFI && allowSnpt 393 when(io.out.head.fire && io.out.head.bits.snapshot) { 394 snapshotCtr := (4 * CommitWidth).U - PopCount(io.out.map(_.fire)) 395 }.elsewhen(io.out.head.fire) { 396 snapshotCtr := Mux(snapshotCtr < PopCount(io.out.map(_.fire)), 0.U, snapshotCtr - PopCount(io.out.map(_.fire))) 397 } 398 399 intFreeList.io.snpt := io.snpt 400 fpFreeList.io.snpt := io.snpt 401 intFreeList.io.snpt.snptEnq := io.out.head.fire && io.out.head.bits.snapshot 402 fpFreeList.io.snpt.snptEnq := io.out.head.fire && io.out.head.bits.snapshot 403 404 /** 405 * Instructions commit: update freelist and rename table 406 */ 407 for (i <- 0 until CommitWidth) { 408 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 409 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 410 411 // I. RAT Update 412 // When redirect happens (mis-prediction), don't update the rename table 413 io.intRenamePorts(i).wen := intSpecWen(i) 414 io.intRenamePorts(i).addr := uops(i).ldest 415 io.intRenamePorts(i).data := io.out(i).bits.pdest 416 417 io.fpRenamePorts(i).wen := fpSpecWen(i) 418 io.fpRenamePorts(i).addr := uops(i).ldest 419 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 420 421 io.vecRenamePorts(i).wen := vecSpecWen(i) 422 io.vecRenamePorts(i).addr := uops(i).ldest 423 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 424 425 // II. Free List Update 426 intFreeList.io.freeReq(i) := io.int_need_free(i) 427 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 428 fpFreeList.io.freeReq(i) := RegNext(commitValid && (needDestRegCommit(Reg_F, io.robCommits.info(i)) || needDestRegCommit(Reg_V, io.robCommits.info(i)))) 429 fpFreeList.io.freePhyReg(i) := Mux(RegNext(needDestRegCommit(Reg_F, io.robCommits.info(i))), io.fp_old_pdest(i), io.vec_old_pdest(i)) 430 } 431 432 /* 433 Debug and performance counters 434 */ 435 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 436 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 437 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 438 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 439 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 440 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 441 ) 442 } 443 444 for ((x,y) <- io.in.zip(io.out)) { 445 printRenameInfo(x, y) 446 } 447 448 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 449 // bad speculation 450 val recStall = io.redirect.valid || io.robCommits.isWalk 451 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.robCommits.isWalk && debugRedirect.debugIsCtrl) 452 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.robCommits.isWalk && debugRedirect.debugIsMemVio) 453 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 454 XSPerfAccumulate("recovery_stall", recStall) 455 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 456 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 457 XSPerfAccumulate("other_recovery_stall", otherRecStall) 458 // freelist stall 459 val notRecStall = !io.out.head.valid && !recStall 460 val intFlStall = notRecStall && inHeadValid && !intFreeList.io.canAllocate 461 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate 462 // other stall 463 val otherStall = notRecStall && !intFlStall && !fpFlStall 464 465 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 466 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 467 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 468 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 469 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 470 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 471 intFlStall -> TopDownCounters.IntFlStall.id.U, 472 fpFlStall -> TopDownCounters.FpFlStall.id.U 473 ) 474 )) 475 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 476 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 477 } 478 479 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 480 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 481 for (i <- 0 until CommitWidth) { 482 val info = io.robCommits.info(i) 483 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 484 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}") 485 } 486 487 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 488 489 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 490 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 491 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 492 XSPerfAccumulate("wait_cycle", !io.in.head.valid && io.out.head.ready) 493 494 // These stall reasons could overlap each other, but we configure the priority as fellows. 495 // walk stall > dispatch stall > int freelist stall > fp freelist stall 496 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 497 private val stallForWalk = inHeadValid && io.robCommits.isWalk 498 private val stallForDispatch = inHeadValid && !io.robCommits.isWalk && !io.out(0).ready 499 private val stallForIntFL = inHeadValid && !io.robCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate 500 private val stallForFpFL = inHeadValid && !io.robCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate 501 XSPerfAccumulate("stall_cycle", inHeadStall) 502 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 503 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 504 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 505 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 506 507 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 508 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 509 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 510 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 511 512 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 513 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 514 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 515 516 val renamePerf = Seq( 517 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 518 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 519 ("rename_stall ", inHeadStall), 520 ("rename_stall_cycle_walk ", inHeadValid && io.robCommits.isWalk), 521 ("rename_stall_cycle_dispatch", inHeadValid && !io.robCommits.isWalk && !io.out(0).ready), 522 ("rename_stall_cycle_int ", inHeadValid && !io.robCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate), 523 ("rename_stall_cycle_fp ", inHeadValid && !io.robCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 524 ) 525 val intFlPerf = intFreeList.getPerfEvents 526 val fpFlPerf = fpFreeList.getPerfEvents 527 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 528 generatePerfEvent() 529} 530