1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.XSInfo 7 8class Rename extends XSModule { 9 val io = IO(new Bundle() { 10 val redirect = Flipped(ValidIO(new Redirect)) 11 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 12 val wbIntResults = Vec(NRIntWritePorts, Flipped(ValidIO(new ExuOutput))) 13 val wbFpResults = Vec(NRFpWritePorts, Flipped(ValidIO(new ExuOutput))) 14 val intRfReadAddr = Vec(NRIntReadPorts, Input(UInt(PhyRegIdxWidth.W))) 15 val fpRfReadAddr = Vec(NRFpReadPorts, Input(UInt(PhyRegIdxWidth.W))) 16 val intPregRdy = Vec(NRIntReadPorts, Output(Bool())) 17 val fpPregRdy = Vec(NRFpReadPorts, Output(Bool())) 18 // set preg to busy when replay 19 val replayPregReq = Vec(ReplayWidth, Input(new ReplayPregReq)) 20 // from decode buffer 21 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 22 // to dispatch1 23 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 24 }) 25 26 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 27 XSInfo( 28 in.valid && in.ready, 29 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 30 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 31 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 32 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 33 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 34 p"old_pdest:${out.bits.old_pdest} " + 35 p"out v:${out.valid} r:${out.ready}\n" 36 ) 37 } 38 39 for((x,y) <- io.in.zip(io.out)){ 40 printRenameInfo(x, y) 41 } 42 43 val fpFreeList, intFreeList = Module(new FreeList).io 44 val fpRat = Module(new RenameTable(float = true)).io 45 val intRat = Module(new RenameTable(float = false)).io 46 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)).io 47 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)).io 48 49 fpFreeList.redirect := io.redirect 50 intFreeList.redirect := io.redirect 51 52 val flush = io.redirect.valid && (io.redirect.bits.isException || io.redirect.bits.isFlushPipe) // TODO: need check by JiaWei 53 fpRat.flush := flush 54 intRat.flush := flush 55 fpBusyTable.flush := flush 56 intBusyTable.flush := flush 57 58 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 59 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 60 } 61 62 val uops = Wire(Vec(RenameWidth, new MicroOp)) 63 64 uops.foreach( uop => { 65// uop.brMask := DontCare 66// uop.brTag := DontCare 67 uop.src1State := DontCare 68 uop.src2State := DontCare 69 uop.src3State := DontCare 70 uop.roqIdx := DontCare 71 uop.diffTestDebugLrScValid := DontCare 72 73 uop.lsroqIdx := DontCare 74 uop.instIsLoad := DontCare 75 uop.lqIdx := DontCare 76 uop.sqIdx := DontCare 77 }) 78 79 var lastReady = WireInit(io.out(0).ready) 80 // debug assert 81 val outRdy = Cat(io.out.map(_.ready)) 82 assert(outRdy===0.U || outRdy.andR()) 83 for(i <- 0 until RenameWidth) { 84 uops(i).cf := io.in(i).bits.cf 85 uops(i).ctrl := io.in(i).bits.ctrl 86 uops(i).brTag := io.in(i).bits.brTag 87 88 val inValid = io.in(i).valid 89 90 // alloc a new phy reg 91 val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits) 92 val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits) 93 fpFreeList.allocReqs(i) := needFpDest && lastReady 94 intFreeList.allocReqs(i) := needIntDest && lastReady 95 val fpCanAlloc = fpFreeList.canAlloc(i) 96 val intCanAlloc = intFreeList.canAlloc(i) 97 val this_can_alloc = Mux( 98 needIntDest, 99 intCanAlloc, 100 Mux( 101 needFpDest, 102 fpCanAlloc, 103 true.B 104 ) 105 ) 106 io.in(i).ready := lastReady && this_can_alloc 107 108 // do checkpoints when a branch inst come 109 for(fl <- Seq(fpFreeList, intFreeList)){ 110 fl.cpReqs(i).valid := inValid 111 fl.cpReqs(i).bits := io.in(i).bits.brTag 112 } 113 114 lastReady = io.in(i).ready 115 116 uops(i).pdest := Mux(needIntDest, 117 intFreeList.pdests(i), 118 Mux( 119 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 120 0.U, fpFreeList.pdests(i) 121 ) 122 ) 123 124 io.out(i).valid := io.in(i).fire() 125 io.out(i).bits := uops(i) 126 127 // write rename table 128 def writeRat(fp: Boolean) = { 129 val rat = if(fp) fpRat else intRat 130 val freeList = if(fp) fpFreeList else intFreeList 131 val busyTable = if(fp) fpBusyTable else intBusyTable 132 // speculative inst write 133 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 134 // walk back write 135 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 136 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 137 138 rat.specWritePorts(i).wen := specWen || walkWen 139 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 140 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 141 142 XSInfo(walkWen, 143 {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" + 144 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 145 ) 146 147 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 148 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 149 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 150 151 XSInfo(rat.archWritePorts(i).wen, 152 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 153 p" pdest:${rat.archWritePorts(i).wdata}\n" 154 ) 155 156 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 157 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 158 159 // set phy reg status to busy 160 busyTable.allocPregs(i).valid := specWen 161 busyTable.allocPregs(i).bits := freeList.pdests(i) 162 } 163 164 writeRat(fp = false) 165 writeRat(fp = true) 166 167 // read rename table 168 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 169 val rat = if(fp) fpRat else intRat 170 val srcCnt = lsrcList.size 171 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 172 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 173 for(k <- 0 until srcCnt+1){ 174 val rportIdx = i * (srcCnt+1) + k 175 if(k != srcCnt){ 176 rat.readPorts(rportIdx).addr := lsrcList(k) 177 psrcVec(k) := rat.readPorts(rportIdx).rdata 178 } else { 179 rat.readPorts(rportIdx).addr := ldest 180 old_pdest := rat.readPorts(rportIdx).rdata 181 } 182 } 183 (psrcVec, old_pdest) 184 } 185 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 186 val ldest = uops(i).ctrl.ldest 187 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 188 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 189 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 190 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 191 uops(i).psrc3 := fpPhySrcVec(2) 192 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 193 } 194 195 196 def updateBusyTable(fp: Boolean) = { 197 val wbResults = if(fp) io.wbFpResults else io.wbIntResults 198 val busyTable = if(fp) fpBusyTable else intBusyTable 199 for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs)){ 200 setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop) 201 setPhyRegRdy.bits := wb.bits.uop.pdest 202 } 203 } 204 205 updateBusyTable(false) 206 updateBusyTable(true) 207 208 intBusyTable.rfReadAddr <> io.intRfReadAddr 209 intBusyTable.pregRdy <> io.intPregRdy 210 for(i <- io.replayPregReq.indices){ 211 intBusyTable.replayPregs(i).valid := io.replayPregReq(i).isInt 212 fpBusyTable.replayPregs(i).valid := io.replayPregReq(i).isFp 213 intBusyTable.replayPregs(i).bits := io.replayPregReq(i).preg 214 fpBusyTable.replayPregs(i).bits := io.replayPregReq(i).preg 215 } 216 fpBusyTable.rfReadAddr <> io.fpRfReadAddr 217 fpBusyTable.pregRdy <> io.fpPregRdy 218} 219