xref: /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala (revision 68eeafa8a2229450b289b44a3e3644291d5b8e3e) 
1package xiangshan.backend.rename
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils.{ParallelOR, XSInfo}
7
8class Rename extends XSModule {
9  val io = IO(new Bundle() {
10    val redirect = Flipped(ValidIO(new Redirect))
11    val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
12    val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput)))
13    val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput)))
14    val intRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W)))
15    val fpRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W)))
16    val intPregRdy = Vec(NRReadPorts, Output(Bool()))
17    val fpPregRdy = Vec(NRReadPorts, Output(Bool()))
18    // from decode buffer
19    val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl)))
20    // to dispatch1
21    val out = Vec(RenameWidth, DecoupledIO(new MicroOp))
22  })
23
24  val isWalk = ParallelOR(io.roqCommits.map(x => x.valid && x.bits.isWalk)).asBool()
25
26  val debug_exception = io.redirect.valid && io.redirect.bits.isException
27  val debug_walk = isWalk
28  val debug_norm = !(debug_exception || debug_walk)
29
30  def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = {
31    XSInfo(
32      debug_norm && in.valid && in.ready,
33      p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " +
34        p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " +
35        p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " +
36        p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " +
37        p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " +
38        p"old_pdest:${out.bits.old_pdest} " +
39        p"out v:${out.valid} r:${out.ready}\n"
40    )
41  }
42
43  for((x,y) <- io.in.zip(io.out)){
44    printRenameInfo(x, y)
45  }
46
47  val fpFreeList, intFreeList = Module(new FreeList).io
48  val fpRat = Module(new RenameTable(float = true)).io
49  val intRat = Module(new RenameTable(float = false)).io
50  val fpBusyTable, intBusyTable = Module(new BusyTable).io
51
52  fpFreeList.redirect := io.redirect
53  intFreeList.redirect := io.redirect
54
55  val flush = io.redirect.valid && io.redirect.bits.isException
56  fpRat.flush := flush
57  intRat.flush := flush
58  fpBusyTable.flush := flush
59  intBusyTable.flush := flush
60
61  def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = {
62    {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)}
63  }
64
65  val uops = Wire(Vec(RenameWidth, new MicroOp))
66
67  uops.foreach( uop => {
68//    uop.brMask := DontCare
69//    uop.brTag := DontCare
70    uop.src1State := DontCare
71    uop.src2State := DontCare
72    uop.src3State := DontCare
73    uop.roqIdx := DontCare
74  })
75
76  var lastReady = WireInit(true.B)
77  for(i <- 0 until RenameWidth) {
78    uops(i).cf := io.in(i).bits.cf
79    uops(i).ctrl := io.in(i).bits.ctrl
80    uops(i).brTag := io.in(i).bits.brTag
81
82    val inValid = io.in(i).valid && !isWalk
83
84    // alloc a new phy reg
85    val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits)
86    val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits)
87    fpFreeList.allocReqs(i) := needFpDest && lastReady && io.out(i).ready
88    intFreeList.allocReqs(i) := needIntDest && lastReady && io.out(i).ready
89    val fpCanAlloc = fpFreeList.canAlloc(i)
90    val intCanAlloc = intFreeList.canAlloc(i)
91    val this_can_alloc = Mux(
92      needIntDest,
93      intCanAlloc,
94      Mux(
95        needFpDest,
96        fpCanAlloc,
97        true.B
98      )
99    )
100    io.in(i).ready := lastReady && io.out(i).ready && this_can_alloc && !isWalk
101
102    // do checkpoints when a branch inst come
103    for(fl <- Seq(fpFreeList, intFreeList)){
104      fl.cpReqs(i).valid := inValid
105      fl.cpReqs(i).bits := io.in(i).bits.brTag
106    }
107
108    lastReady = io.in(i).ready
109
110    uops(i).pdest := Mux(needIntDest,
111      intFreeList.pdests(i),
112      Mux(
113        uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen,
114        0.U, fpFreeList.pdests(i)
115      )
116    )
117
118    io.out(i).valid := io.in(i).fire()
119    io.out(i).bits := uops(i)
120
121    // write rename table
122    def writeRat(fp: Boolean) = {
123      val rat = if(fp) fpRat else intRat
124      val freeList = if(fp) fpFreeList else intFreeList
125      val busyTable = if(fp) fpBusyTable else intBusyTable
126      // speculative inst write
127      val specWen = freeList.allocReqs(i) && freeList.canAlloc(i)
128      // walk back write
129      val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop)
130      val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk
131
132      rat.specWritePorts(i).wen := specWen || walkWen
133      rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest)
134      rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest)
135
136      busyTable.wbPregs(NRWritePorts + i).valid := walkWen
137      busyTable.wbPregs(NRWritePorts + i).bits := io.roqCommits(i).bits.uop.pdest
138
139      XSInfo(walkWen,
140        {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" +
141          p" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
142      )
143
144      rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk
145      rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest
146      rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest
147
148      XSInfo(rat.archWritePorts(i).wen,
149        {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" +
150          p" pdest:${rat.archWritePorts(i).wdata}\n"
151      )
152
153      freeList.deallocReqs(i) := rat.archWritePorts(i).wen
154      freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest
155
156      // set phy reg status to busy
157      busyTable.allocPregs(i).valid := specWen
158      busyTable.allocPregs(i).bits := freeList.pdests(i)
159    }
160
161    writeRat(fp = false)
162    writeRat(fp = true)
163
164    // read rename table
165    def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = {
166      val rat = if(fp) fpRat else intRat
167      val srcCnt = lsrcList.size
168      val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W)))
169      val old_pdest = Wire(UInt(PhyRegIdxWidth.W))
170      for(k <- 0 until srcCnt+1){
171        val rportIdx = i * (srcCnt+1) + k
172        if(k != srcCnt){
173          rat.readPorts(rportIdx).addr := lsrcList(k)
174          psrcVec(k) := rat.readPorts(rportIdx).rdata
175        } else {
176          rat.readPorts(rportIdx).addr := ldest
177          old_pdest := rat.readPorts(rportIdx).rdata
178        }
179      }
180      (psrcVec, old_pdest)
181    }
182    val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3)
183    val ldest = uops(i).ctrl.ldest
184    val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false)
185    val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true)
186    uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0))
187    uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1))
188    uops(i).psrc3 := fpPhySrcVec(2)
189    uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest)
190  }
191
192
193  def updateBusyTable(fp: Boolean) = {
194    val wbResults = if(fp) io.wbFpResults else io.wbIntResults
195    val busyTable = if(fp) fpBusyTable else intBusyTable
196    for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs.take(NRWritePorts))){
197      setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop)
198      setPhyRegRdy.bits := wb.bits.uop.pdest
199    }
200  }
201
202  updateBusyTable(false)
203  updateBusyTable(true)
204
205  intBusyTable.rfReadAddr <> io.intRfReadAddr
206  intBusyTable.pregRdy <> io.intPregRdy
207  fpBusyTable.rfReadAddr <> io.fpRfReadAddr
208  fpBusyTable.pregRdy <> io.fpPregRdy
209}
210