1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31 32class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 33 34 // params alias 35 private val numRegSrc = backendParams.numRegSrc 36 private val numVecRegSrc = backendParams.numVecRegSrc 37 private val numVecRatPorts = numVecRegSrc 38 39 println(s"[Rename] numRegSrc: $numRegSrc") 40 41 val io = IO(new Bundle() { 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val rabCommits = Input(new RabCommitIO) 44 // from decode 45 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 46 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 47 // ssit read result 48 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 49 // waittable read result 50 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 51 // to rename table 52 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 53 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 54 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 55 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 58 // from rename table 59 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 60 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 61 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 62 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 63 // to dispatch1 64 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 65 // for snapshots 66 val snpt = Input(new SnapshotPort) 67 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 68 val snptIsFull= Input(Bool()) 69 // debug arch ports 70 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 71 val debug_vconfig_rat = if (backendParams.debugEn) Some(Input(UInt(PhyRegIdxWidth.W))) else None 72 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 73 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 74 // perf only 75 val stallReason = new Bundle { 76 val in = Flipped(new StallReasonIO(RenameWidth)) 77 val out = new StallReasonIO(RenameWidth) 78 } 79 }) 80 81 // io alias 82 private val dispatchCanAcc = io.out.head.ready 83 84 val compressUnit = Module(new CompressUnit()) 85 // create free list and rat 86 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 87 val fpFreeList = Module(new StdFreeList(FpPhyRegs - FpLogicRegs, FpLogicRegs, Reg_F)) 88 val vecFreeList = Module(new StdFreeList(VfPhyRegs - VecLogicRegs, VecLogicRegs, Reg_V)) 89 90 intFreeList.io.commit <> io.rabCommits 91 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 92 fpFreeList.io.commit <> io.rabCommits 93 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 94 vecFreeList.io.commit <> io.rabCommits 95 vecFreeList.io.debug_rat.foreach(_ <> io.debug_vec_rat.get) 96 97 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 98 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 99 case Reg_I => x.rfWen && x.ldest =/= 0.U 100 case Reg_F => x.fpWen 101 case Reg_V => x.vecWen 102 } 103 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 104 reg_t match { 105 case Reg_I => x.rfWen 106 case Reg_F => x.fpWen 107 case Reg_V => x.vecWen 108 } 109 } 110 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 111 reg_t match { 112 case Reg_I => x.rfWen && x.ldest =/= 0.U 113 case Reg_F => x.fpWen 114 case Reg_V => x.vecWen 115 } 116 } 117 118 // connect [redirect + walk] ports for fp & vec & int free list 119 Seq(fpFreeList, vecFreeList, intFreeList).foreach { case fl => 120 fl.io.redirect := io.redirect.valid 121 fl.io.walk := io.rabCommits.isWalk 122 } 123 // only when all free list and dispatch1 has enough space can we do allocation 124 // when isWalk, freelist can definitely allocate 125 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 126 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && vecFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 127 vecFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 128 129 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ vec free list ready ++ not walk 130 val canOut = dispatchCanAcc && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !io.rabCommits.isWalk 131 132 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 133 sink.valid := source.valid 134 sink.bits := source.bits 135 } 136 val needRobFlags = compressUnit.io.out.needRobFlags 137 val instrSizesVec = compressUnit.io.out.instrSizes 138 val compressMasksVec = compressUnit.io.out.masks 139 140 // speculatively assign the instruction with an robIdx 141 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 142 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 143 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 144 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 145 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 146 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 147 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 148 robIdxHead := robIdxHeadNext 149 150 /** 151 * Rename: allocate free physical register and update rename table 152 */ 153 val uops = Wire(Vec(RenameWidth, new DynInst)) 154 uops.foreach( uop => { 155 uop.srcState := DontCare 156 uop.debugInfo := DontCare 157 uop.lqIdx := DontCare 158 uop.sqIdx := DontCare 159 uop.waitForRobIdx := DontCare 160 uop.singleStep := DontCare 161 uop.snapshot := DontCare 162 uop.srcLoadDependency := DontCare 163 uop.numLsElem := DontCare 164 }) 165 166 val needVecDest = Wire(Vec(RenameWidth, Bool())) 167 val needFpDest = Wire(Vec(RenameWidth, Bool())) 168 val needIntDest = Wire(Vec(RenameWidth, Bool())) 169 val hasValid = Cat(io.in.map(_.valid)).orR 170 private val inHeadValid = io.in.head.valid 171 172 val isMove = Wire(Vec(RenameWidth, Bool())) 173 isMove zip io.in.map(_.bits) foreach { 174 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 175 } 176 177 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 178 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 179 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 180 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 181 182 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 183 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 184 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 185 186 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 187 188 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 189 190 // uop calculation 191 for (i <- 0 until RenameWidth) { 192 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 193 194 // update cf according to ssit result 195 uops(i).storeSetHit := io.ssit(i).valid 196 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 197 uops(i).ssid := io.ssit(i).ssid 198 199 // update cf according to waittable result 200 uops(i).loadWaitBit := io.waittable(i) 201 202 uops(i).replayInst := false.B // set by IQ or MemQ 203 // alloc a new phy reg 204 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 205 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 206 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 207 if (i < RabCommitWidth) { 208 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 209 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 210 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 211 walkIsMove(i) := io.rabCommits.info(i).isMove 212 } 213 fpFreeList.io.allocateReq(i) := needFpDest(i) 214 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) 215 vecFreeList.io.allocateReq(i) := needVecDest(i) 216 vecFreeList.io.walkReq(i) := walkNeedVecDest(i) 217 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 218 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 219 220 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 221 io.in(i).ready := !hasValid || canOut 222 223 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 224 uops(i).instrSize := instrSizesVec(i) 225 when(isMove(i)) { 226 uops(i).numUops := 0.U 227 uops(i).numWB := 0.U 228 } 229 if (i > 0) { 230 when(!needRobFlags(i - 1)) { 231 uops(i).firstUop := false.B 232 uops(i).ftqPtr := uops(i - 1).ftqPtr 233 uops(i).ftqOffset := uops(i - 1).ftqOffset 234 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 235 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 236 } 237 } 238 when(!needRobFlags(i)) { 239 uops(i).lastUop := false.B 240 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 241 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 242 } 243 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 244 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 245 // vector instructions' uopSplitType cannot be UopSplitType.SCA_SIM 246 uops(i).dirtyVs := (compressMasksVec(i) & Cat(io.in.map(_.bits.uopSplitType =/= UopSplitType.SCA_SIM).reverse)).orR 247 248 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 249 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 250 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 251 uops(i).psrc(3) := io.vecReadPorts(i)(3) 252 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 253 254 // int psrc2 should be bypassed from next instruction if it is fused 255 if (i < RenameWidth - 1) { 256 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 257 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 258 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 259 uops(i).psrc(1) := 0.U 260 } 261 } 262 uops(i).eliminatedMove := isMove(i) 263 264 // update pdest 265 uops(i).pdest := MuxCase(0.U, Seq( 266 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 267 needFpDest(i) -> fpFreeList.io.allocatePhyReg(i), 268 needVecDest(i) -> vecFreeList.io.allocatePhyReg(i), 269 )) 270 271 // Assign performance counters 272 uops(i).debugInfo.renameTime := GTimer() 273 274 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && !io.rabCommits.isWalk 275 io.out(i).bits := uops(i) 276 // Todo: move these shit in decode stage 277 // dirty code for fence. The lsrc is passed by imm. 278 when (io.out(i).bits.fuType === FuType.fence.U) { 279 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 280 } 281 282 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 283// when (io.in(i).bits.isSoftPrefetch) { 284// io.out(i).bits.fuType := FuType.ldu.U 285// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 286// io.out(i).bits.selImm := SelImm.IMM_S 287// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 288// } 289 290 // dirty code for lui+addi(w) fusion 291 if (i < RenameWidth - 1) { 292 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 293 when (fused_lui32) { 294 val lui_imm = io.in(i).bits.imm(19, 0) 295 val add_imm = io.in(i + 1).bits.imm(11, 0) 296 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 297 io.out(i).bits.imm := Cat(lui_imm, add_imm) 298 } 299 } 300 301 // write speculative rename table 302 // we update rat later inside commit code 303 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 304 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 305 vecSpecWen(i) := needVecDest(i) && vecFreeList.io.canAllocate && vecFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 306 307 308 if (i < RabCommitWidth) { 309 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 310 walkPdest(i) := io.rabCommits.info(i).pdest 311 } else { 312 walkPdest(i) := io.out(i).bits.pdest 313 } 314 } 315 316 /** 317 * How to set psrc: 318 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 319 * - default: psrc from RAT 320 * How to set pdest: 321 * - Mux(isMove, psrc, pdest_from_freelist). 322 * 323 * The critical path of rename lies here: 324 * When move elimination is enabled, we need to update the rat with psrc. 325 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 326 * 327 * If we expand these logic for pdest(N): 328 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 329 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 330 * Mux(bypass(N, N - 2), pdest(N - 2), 331 * ... 332 * Mux(bypass(N, 0), pdest(0), 333 * rat_out(N))...)), 334 * freelist_out(N)) 335 */ 336 // a simple functional model for now 337 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 338 339 // psrc(n) + pdest(1) 340 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 341 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 342 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 343 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 344 for (i <- 1 until RenameWidth) { 345 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 346 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 347 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 348 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 349 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 350 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 351 val indexMatch = in.bits.ldest === t 352 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 353 indexMatch && writeMatch 354 } 355 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 356 } 357 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 358 (z, next) => Mux(next._2, next._1, z) 359 } 360 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 361 (z, next) => Mux(next._2, next._1, z) 362 } 363 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 364 (z, next) => Mux(next._2, next._1, z) 365 } 366 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 367 (z, next) => Mux(next._2, next._1, z) 368 } 369 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 370 (z, next) => Mux(next._2, next._1, z) 371 } 372 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 373 374 // Todo: better implementation for fields reuse 375 // For fused-lui-load, load.src(0) is replaced by the imm. 376 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 377 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 378 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 379 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 380 when (fused_lui_load) { 381 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 382 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 383 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 384 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 385 io.out(i).bits.srcType(0) := SrcType.imm 386 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 387 } 388 389 } 390 391 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 392 val lastCycleCreateSnpt = RegInit(false.B) 393 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 394 val sameSnptDistance = (RobCommitWidth * 4).U 395 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 396 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 397 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 398 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 399 if(backendParams.debugEn){ 400 dontTouch(robIdxHeadNext) 401 dontTouch(notInSameSnpt) 402 dontTouch(genSnapshot) 403 } 404 intFreeList.io.snpt := io.snpt 405 fpFreeList.io.snpt := io.snpt 406 vecFreeList.io.snpt := io.snpt 407 intFreeList.io.snpt.snptEnq := genSnapshot 408 fpFreeList.io.snpt.snptEnq := genSnapshot 409 vecFreeList.io.snpt.snptEnq := genSnapshot 410 411 /** 412 * Instructions commit: update freelist and rename table 413 */ 414 for (i <- 0 until RabCommitWidth) { 415 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 416 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 417 418 // I. RAT Update 419 // When redirect happens (mis-prediction), don't update the rename table 420 io.intRenamePorts(i).wen := intSpecWen(i) 421 io.intRenamePorts(i).addr := uops(i).ldest 422 io.intRenamePorts(i).data := io.out(i).bits.pdest 423 424 io.fpRenamePorts(i).wen := fpSpecWen(i) 425 io.fpRenamePorts(i).addr := uops(i).ldest 426 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 427 428 io.vecRenamePorts(i).wen := vecSpecWen(i) 429 io.vecRenamePorts(i).addr := uops(i).ldest 430 io.vecRenamePorts(i).data := vecFreeList.io.allocatePhyReg(i) 431 432 // II. Free List Update 433 intFreeList.io.freeReq(i) := io.int_need_free(i) 434 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 435 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_F, io.rabCommits.info(i))) 436 fpFreeList.io.freePhyReg(i) := io.fp_old_pdest(i) 437 vecFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V, io.rabCommits.info(i))) 438 vecFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 439 } 440 441 /* 442 Debug and performance counters 443 */ 444 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 445 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 446 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 447 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 448 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 449 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 450 ) 451 } 452 453 for ((x,y) <- io.in.zip(io.out)) { 454 printRenameInfo(x, y) 455 } 456 457 io.out.map { case x => 458 when(x.valid && x.bits.rfWen){ 459 assert(x.bits.ldest =/= 0.U, "rfWen cannot be 1 when Int regfile ldest is 0") 460 } 461 } 462 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 463 // bad speculation 464 val recStall = io.redirect.valid || io.rabCommits.isWalk 465 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 466 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 467 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 468 XSPerfAccumulate("recovery_stall", recStall) 469 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 470 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 471 XSPerfAccumulate("other_recovery_stall", otherRecStall) 472 // freelist stall 473 val notRecStall = !io.out.head.valid && !recStall 474 val intFlStall = notRecStall && inHeadValid && !intFreeList.io.canAllocate 475 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !fpFreeList.io.canAllocate 476 val vecFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !vecFreeList.io.canAllocate 477 // other stall 478 val otherStall = notRecStall && !intFlStall && !fpFlStall && !vecFlStall 479 480 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 481 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 482 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 483 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 484 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 485 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 486 intFlStall -> TopDownCounters.IntFlStall.id.U, 487 fpFlStall -> TopDownCounters.FpFlStall.id.U, 488 vecFlStall -> TopDownCounters.VecFlStall.id.U, 489 ) 490 )) 491 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 492 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 493 } 494 495 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 496 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 497 for (i <- 0 until RabCommitWidth) { 498 val info = io.rabCommits.info(i) 499 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 500 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}") 501 } 502 503 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 504 505 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 506 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 507 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 508 XSPerfAccumulate("wait_cycle", !io.in.head.valid && dispatchCanAcc) 509 510 // These stall reasons could overlap each other, but we configure the priority as fellows. 511 // walk stall > dispatch stall > int freelist stall > fp freelist stall 512 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 513 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 514 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc 515 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && !intFreeList.io.canAllocate 516 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !fpFreeList.io.canAllocate 517 private val stallForVecFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !vecFreeList.io.canAllocate 518 XSPerfAccumulate("stall_cycle", inHeadStall) 519 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 520 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 521 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 522 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 523 XSPerfAccumulate("stall_cycle_vec", stallForVecFL) 524 525 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 526 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 527 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 528 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 529 530 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 531 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 532 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 533 534 val renamePerf = Seq( 535 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 536 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 537 ("rename_stall ", inHeadStall), 538 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 539 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc), 540 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && !intFreeList.io.canAllocate), 541 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 542 ("rename_stall_cycle_vec ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !vecFreeList.io.canAllocate), 543 ) 544 val intFlPerf = intFreeList.getPerfEvents 545 val fpFlPerf = fpFreeList.getPerfEvents 546 val vecFlPerf = vecFreeList.getPerfEvents 547 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf 548 generatePerfEvent() 549} 550