1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import xiangshan.backend.roq.RoqPtr 8import xiangshan.backend.dispatch.PreDispatchInfo 9 10class RenameBypassInfo extends XSBundle { 11 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 14 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 15 val move_eliminated_src1 = Vec(RenameWidth-1, Bool()) 16 val move_eliminated_src2 = Vec(RenameWidth-1, Bool()) 17} 18 19class Rename extends XSModule with HasCircularQueuePtrHelper { 20 val io = IO(new Bundle() { 21 val redirect = Flipped(ValidIO(new Redirect)) 22 val flush = Input(Bool()) 23 val roqCommits = Flipped(new RoqCommitIO) 24 // from decode buffer 25 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 26 // to dispatch1 27 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 28 val renameBypass = Output(new RenameBypassInfo) 29 val dispatchInfo = Output(new PreDispatchInfo) 30 val csrCtrl = Flipped(new CustomCSRCtrlIO) 31 }) 32 33 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 34 XSInfo( 35 in.valid && in.ready, 36 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 37 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 38 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 39 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 40 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 41 p"old_pdest:${out.bits.old_pdest} " + 42 p"out v:${out.valid} r:${out.ready}\n" 43 ) 44 } 45 46 for((x,y) <- io.in.zip(io.out)){ 47 printRenameInfo(x, y) 48 } 49 50 val intFreeList, fpFreeList = Module(new FreeList).io 51 val intRat = Module(new RenameTable(float = false)).io 52 val fpRat = Module(new RenameTable(float = true)).io 53 val allPhyResource = Seq((intRat, intFreeList, false), (fpRat, fpFreeList, true)) 54 55 allPhyResource.map{ case (rat, freelist, _) => 56 rat.redirect := io.redirect.valid 57 rat.flush := io.flush 58 rat.walkWen := io.roqCommits.isWalk 59 freelist.redirect := io.redirect.valid 60 freelist.flush := io.flush 61 freelist.walk.valid := io.roqCommits.isWalk 62 } 63 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 64 65 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 66 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 67 } 68 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 69 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 70 } 71 fpFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 72 intFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(false, i)}) 73 // walk has higher priority than allocation and thus we don't use isWalk here 74 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 75 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 76 77 // speculatively assign the instruction with an roqIdx 78 val validCount = PopCount(io.in.map(_.valid)) 79 val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr)) 80 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 81 val roqIdxHeadNext = Mux(io.flush, 82 0.U.asTypeOf(new RoqPtr), 83 Mux(io.redirect.valid, 84 io.redirect.bits.roqIdx, 85 Mux(lastCycleMisprediction, 86 roqIdxHead + 1.U, 87 Mux(canOut, roqIdxHead + validCount, roqIdxHead)) 88 ) 89 ) 90 roqIdxHead := roqIdxHeadNext 91 92 /** 93 * Rename: allocate free physical register and update rename table 94 */ 95 val uops = Wire(Vec(RenameWidth, new MicroOp)) 96 97 uops.foreach( uop => { 98// uop.brMask := DontCare 99// uop.brTag := DontCare 100 uop.src1State := DontCare 101 uop.src2State := DontCare 102 uop.src3State := DontCare 103 uop.roqIdx := DontCare 104 uop.diffTestDebugLrScValid := DontCare 105 uop.debugInfo := DontCare 106 uop.lqIdx := DontCare 107 uop.sqIdx := DontCare 108 }) 109 110 val needFpDest = Wire(Vec(RenameWidth, Bool())) 111 val needIntDest = Wire(Vec(RenameWidth, Bool())) 112 val hasValid = Cat(io.in.map(_.valid)).orR 113 for (i <- 0 until RenameWidth) { 114 uops(i).cf := io.in(i).bits.cf 115 uops(i).ctrl := io.in(i).bits.ctrl 116 117 val inValid = io.in(i).valid 118 119 // alloc a new phy reg 120 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 121 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 122 fpFreeList.req.allocReqs(i) := needFpDest(i) 123 intFreeList.req.allocReqs(i) := needIntDest(i) 124 125 io.in(i).ready := !hasValid || canOut 126 127 // do checkpoints when a branch inst come 128 // for(fl <- Seq(fpFreeList, intFreeList)){ 129 // fl.cpReqs(i).valid := inValid 130 // fl.cpReqs(i).bits := io.in(i).bits.brTag 131 // } 132 133 uops(i).pdest := Mux(needIntDest(i), 134 intFreeList.req.pdests(i), 135 Mux( 136 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 137 0.U, fpFreeList.req.pdests(i) 138 ) 139 ) 140 141 uops(i).roqIdx := roqIdxHead + i.U 142 143 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 144 io.out(i).bits := uops(i) 145 146 // write speculative rename table 147 allPhyResource.map{ case (rat, freelist, _) => 148 val specWen = freelist.req.allocReqs(i) && freelist.req.canAlloc && freelist.req.doAlloc && !io.roqCommits.isWalk 149 150 rat.specWritePorts(i).wen := specWen 151 rat.specWritePorts(i).addr := uops(i).ctrl.ldest 152 rat.specWritePorts(i).wdata := freelist.req.pdests(i) 153 154 freelist.deallocReqs(i) := specWen 155 } 156 157 // read rename table 158 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 159 val rat = if(fp) fpRat else intRat 160 val srcCnt = lsrcList.size 161 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 162 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 163 for(k <- 0 until srcCnt+1){ 164 val rportIdx = i * (srcCnt+1) + k 165 if(k != srcCnt){ 166 rat.readPorts(rportIdx).addr := lsrcList(k) 167 psrcVec(k) := rat.readPorts(rportIdx).rdata 168 } else { 169 rat.readPorts(rportIdx).addr := ldest 170 old_pdest := rat.readPorts(rportIdx).rdata 171 } 172 } 173 (psrcVec, old_pdest) 174 } 175 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 176 val ldest = uops(i).ctrl.ldest 177 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 178 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 179 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 180 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 181 uops(i).psrc3 := fpPhySrcVec(2) 182 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 183 } 184 185 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 186 // Instead, we determine whether there're some dependences between the valid instructions. 187 for (i <- 1 until RenameWidth) { 188 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 189 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 190 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 191 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 192 }).reverse) 193 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 194 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 195 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 196 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 197 }).reverse) 198 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 199 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 200 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 201 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 202 }).reverse) 203 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 204 val fpMatch = needFpDest(j) && needFpDest(i) 205 val intMatch = needIntDest(j) && needIntDest(i) 206 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 207 }).reverse) 208 io.renameBypass.move_eliminated_src1(i-1) := 209 // the producer move instruction writes to non-zero register 210 io.in(i-1).bits.ctrl.isMove && io.in(i-1).bits.ctrl.ldest =/= 0.U && 211 // the consumer instruction uses the move's destination register 212 io.in(i).bits.ctrl.src1Type === SrcType.reg && io.in(i).bits.ctrl.lsrc1 === io.in(i-1).bits.ctrl.ldest && 213 // CSR control (by srnctl) 214 io.csrCtrl.move_elim_enable 215 io.renameBypass.move_eliminated_src2(i-1) := 216 // the producer move instruction writes to non-zero register 217 io.in(i-1).bits.ctrl.isMove && io.in(i-1).bits.ctrl.ldest =/= 0.U && 218 // the consumer instruction uses the move's destination register 219 io.in(i).bits.ctrl.src2Type === SrcType.reg && io.in(i).bits.ctrl.lsrc2 === io.in(i-1).bits.ctrl.ldest && 220 // CSR control (by srnctl) 221 io.csrCtrl.move_elim_enable 222 } 223 224 val isLs = VecInit(uops.map(uop => FuType.isLoadStore(uop.ctrl.fuType))) 225 val isStore = VecInit(uops.map(uop => FuType.isStoreExu(uop.ctrl.fuType))) 226 val isAMO = VecInit(uops.map(uop => FuType.isAMO(uop.ctrl.fuType))) 227 io.dispatchInfo.lsqNeedAlloc := VecInit((0 until RenameWidth).map(i => 228 Mux(isLs(i), Mux(isStore(i) && !isAMO(i), 2.U, 1.U), 0.U))) 229 230 /** 231 * Instructions commit: update freelist and rename table 232 */ 233 for (i <- 0 until CommitWidth) { 234 if (i >= RenameWidth) { 235 allPhyResource.map{ case (rat, _, _) => 236 rat.specWritePorts(i).wen := false.B 237 rat.specWritePorts(i).addr := DontCare 238 rat.specWritePorts(i).wdata := DontCare 239 } 240 } 241 242 allPhyResource.map{ case (rat, freelist, fp) => 243 // walk back write 244 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 245 246 when (commitDestValid && io.roqCommits.isWalk) { 247 rat.specWritePorts(i).wen := true.B 248 rat.specWritePorts(i).addr := io.roqCommits.info(i).ldest 249 rat.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 250 XSInfo({if(fp) p"fp" else p"int "} + p"walk: " + 251 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n") 252 } 253 254 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 255 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 256 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 257 258 XSInfo(rat.archWritePorts(i).wen, 259 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 260 p" pdest:${rat.archWritePorts(i).wdata}\n" 261 ) 262 263 freelist.deallocReqs(i) := rat.archWritePorts(i).wen 264 freelist.deallocPregs(i) := io.roqCommits.info(i).old_pdest 265 } 266 } 267 268 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 269 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 270 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 271 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 272 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 273 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && !intFreeList.req.canAlloc && !io.roqCommits.isWalk) 274 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && io.roqCommits.isWalk) 275 276} 277