1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.utils.{ParallelOR, XSInfo} 7 8class Rename extends XSModule { 9 val io = IO(new Bundle() { 10 val redirect = Flipped(ValidIO(new Redirect)) 11 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 12 val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 13 val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 14 val intRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 15 val fpRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 16 val intPregRdy = Vec(NRReadPorts, Output(Bool())) 17 val fpPregRdy = Vec(NRReadPorts, Output(Bool())) 18 // from decode buffer 19 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 20 // to dispatch1 21 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 22 }) 23 24 val isWalk = ParallelOR(io.roqCommits.map(x => x.valid && x.bits.isWalk)).asBool() 25 26 val debug_exception = io.redirect.valid && io.redirect.bits.isException 27 val debug_walk = isWalk 28 val debug_norm = !(debug_exception || debug_walk) 29 30 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 31 XSInfo( 32 debug_norm, 33 p"pc:${Hexadecimal(in.bits.cf.pc)} v:${in.valid} rdy:${in.ready} " + 34 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 35 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 36 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 37 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 38 p"old_pdest:${out.bits.old_pdest}\n" 39 ) 40 } 41 42 for((x,y) <- io.in.zip(io.out)){ 43 printRenameInfo(x, y) 44 } 45 46 val fpFreeList, intFreeList = Module(new FreeList).io 47 val fpRat = Module(new RenameTable(float = true)).io 48 val intRat = Module(new RenameTable(float = false)).io 49 val fpBusyTable, intBusyTable = Module(new BusyTable).io 50 51 fpFreeList.redirect := io.redirect 52 intFreeList.redirect := io.redirect 53 54 val flush = io.redirect.valid && io.redirect.bits.isException 55 fpRat.flush := flush 56 intRat.flush := flush 57 fpBusyTable.flush := flush 58 intBusyTable.flush := flush 59 60 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 61 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 62 } 63 64 val uops = Wire(Vec(RenameWidth, new MicroOp)) 65 66 uops.foreach( uop => { 67// uop.brMask := DontCare 68// uop.brTag := DontCare 69 uop.src1State := DontCare 70 uop.src2State := DontCare 71 uop.src3State := DontCare 72 uop.roqIdx := DontCare 73 }) 74 75 var last_can_alloc = WireInit(true.B) 76 for(i <- 0 until RenameWidth) { 77 uops(i).cf := io.in(i).bits.cf 78 uops(i).ctrl := io.in(i).bits.ctrl 79 uops(i).brMask := io.in(i).bits.brMask 80 uops(i).brTag := io.in(i).bits.brTag 81 82 val inValid = io.in(i).valid && !isWalk 83 84 // alloc a new phy reg 85 val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits) 86 val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits) 87 fpFreeList.allocReqs(i) := needFpDest && last_can_alloc && io.out(i).ready 88 intFreeList.allocReqs(i) := needIntDest && last_can_alloc && io.out(i).ready 89 val fpCanAlloc = fpFreeList.canAlloc(i) 90 val intCanAlloc = intFreeList.canAlloc(i) 91 val this_can_alloc = Mux(needIntDest, intCanAlloc, fpCanAlloc) 92 io.in(i).ready := this_can_alloc && !isWalk 93 last_can_alloc = last_can_alloc && this_can_alloc 94 uops(i).pdest := Mux(needIntDest, intFreeList.pdests(i), fpFreeList.pdests(i)) 95 uops(i).freelistAllocPtr := Mux(needIntDest, intFreeList.allocPtrs(i), fpFreeList.allocPtrs(i)) 96 97 io.out(i).valid := io.in(i).fire() 98 io.out(i).bits := uops(i) 99 100 // write rename table 101 def writeRat(fp: Boolean) = { 102 val rat = if(fp) fpRat else intRat 103 val freeList = if(fp) fpFreeList else intFreeList 104 val busyTable = if(fp) fpBusyTable else intBusyTable 105 // speculative inst write 106 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 107 // walk back write 108 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 109 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 110 111 rat.specWritePorts(i).wen := specWen || walkWen 112 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 113 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 114 115 XSInfo(walkWen, 116 {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" + 117 p" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 118 ) 119 120 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 121 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 122 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 123 124 XSInfo(rat.archWritePorts(i).wen, 125 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 126 p" pdest:${rat.archWritePorts(i).wdata}\n" 127 ) 128 129 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 130 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 131 132 // set phy reg status to busy 133 busyTable.allocPregs(i).valid := specWen 134 busyTable.allocPregs(i).bits := freeList.pdests(i) 135 } 136 137 writeRat(fp = false) 138 writeRat(fp = true) 139 140 // read rename table 141 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 142 val rat = if(fp) fpRat else intRat 143 val srcCnt = lsrcList.size 144 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 145 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 146 for(k <- 0 until srcCnt+1){ 147 val rportIdx = i * (srcCnt+1) + k 148 if(k != srcCnt){ 149 rat.readPorts(rportIdx).addr := lsrcList(k) 150 psrcVec(k) := rat.readPorts(rportIdx).rdata 151 } else { 152 rat.readPorts(rportIdx).addr := ldest 153 old_pdest := rat.readPorts(rportIdx).rdata 154 } 155 } 156 (psrcVec, old_pdest) 157 } 158 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 159 val ldest = uops(i).ctrl.ldest 160 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 161 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 162 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 163 uops(i).psrc2 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 164 uops(i).psrc3 := fpPhySrcVec(2) 165 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 166 } 167 168 169 def updateBusyTable(fp: Boolean) = { 170 val wbResults = if(fp) io.wbFpResults else io.wbIntResults 171 val busyTable = if(fp) fpBusyTable else intBusyTable 172 for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs)){ 173 setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop) 174 setPhyRegRdy.bits := wb.bits.uop.pdest 175 } 176 } 177 178 updateBusyTable(false) 179 updateBusyTable(true) 180 181 intBusyTable.rfReadAddr <> io.intRfReadAddr 182 intBusyTable.pregRdy <> io.intPregRdy 183 fpBusyTable.rfReadAddr <> io.fpRfReadAddr 184 fpBusyTable.pregRdy <> io.fpPregRdy 185} 186