1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend.rob.RobPtr 25import xiangshan.backend.dispatch.PreDispatchInfo 26import xiangshan.backend.rename.freelist._ 27 28class Rename(implicit p: Parameters) extends XSModule { 29 val io = IO(new Bundle() { 30 val redirect = Flipped(ValidIO(new Redirect)) 31 val robCommits = Flipped(new RobCommitIO) 32 // from decode 33 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 34 // to rename table 35 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 36 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 37 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 38 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 39 // to dispatch1 40 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 41 val dispatchInfo = Output(new PreDispatchInfo) 42 }) 43 44 // create free list and rat 45 val intFreeList = Module(new MEFreeList(MEFreeListSize)) 46 val intRefCounter = Module(new RefCounter(MEFreeListSize)) 47 val fpFreeList = Module(new StdFreeList(StdFreeListSize)) 48 49 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 50 val isIntDest = io.in.map(in => in.bits.ctrl.rfWen && in.bits.ctrl.ldest =/= 0.U) 51 val isFpDest = io.in.map(_.bits.ctrl.fpWen) 52 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 53 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 54 } 55 def needDestRegCommit[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 56 // TODO: why this ldest? 57 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 58 } 59 60 // connect [redirect + walk] ports for __float point__ & __integer__ free list 61 Seq((fpFreeList, true), (intFreeList, false)).foreach{ case (fl, isFp) => 62 fl.io.redirect := io.redirect.valid 63 fl.io.walk := io.robCommits.isWalk 64 // when isWalk, use stepBack to restore head pointer of free list 65 // (if ME enabled, stepBack of intFreeList should be useless thus optimized out) 66 fl.io.stepBack := PopCount(io.robCommits.valid.zip(io.robCommits.info).map{case (v, i) => v && needDestRegCommit(isFp, i)}) 67 } 68 // walk has higher priority than allocation and thus we don't use isWalk here 69 // only when both fp and int free list and dispatch1 has enough space can we do allocation 70 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready 71 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready 72 73 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 74 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 75 76 77 // speculatively assign the instruction with an robIdx 78 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 79 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 80 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 81 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 82 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 83 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 84 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 85 robIdxHead := robIdxHeadNext 86 87 /** 88 * Rename: allocate free physical register and update rename table 89 */ 90 val uops = Wire(Vec(RenameWidth, new MicroOp)) 91 uops.foreach( uop => { 92 uop.srcState(0) := DontCare 93 uop.srcState(1) := DontCare 94 uop.srcState(2) := DontCare 95 uop.robIdx := DontCare 96 uop.diffTestDebugLrScValid := DontCare 97 uop.debugInfo := DontCare 98 uop.lqIdx := DontCare 99 uop.sqIdx := DontCare 100 }) 101 102 val needFpDest = Wire(Vec(RenameWidth, Bool())) 103 val needIntDest = Wire(Vec(RenameWidth, Bool())) 104 val hasValid = Cat(io.in.map(_.valid)).orR 105 106 val isMove = io.in.map(_.bits.ctrl.isMove) 107 val intPsrc = Wire(Vec(RenameWidth, UInt())) 108 109 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 110 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 111 112 // uop calculation 113 for (i <- 0 until RenameWidth) { 114 uops(i).cf := io.in(i).bits.cf 115 uops(i).ctrl := io.in(i).bits.ctrl 116 117 val inValid = io.in(i).valid 118 119 // alloc a new phy reg 120 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 121 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 122 fpFreeList.io.allocateReq(i) := needFpDest(i) 123 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 124 125 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 126 io.in(i).ready := !hasValid || canOut 127 128 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 129 130 val intPhySrcVec = io.intReadPorts(i).take(2) 131 val intOldPdest = io.intReadPorts(i).last 132 intPsrc(i) := intPhySrcVec(0) 133 val fpPhySrcVec = io.fpReadPorts(i).take(3) 134 val fpOldPdest = io.fpReadPorts(i).last 135 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 136 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 137 uops(i).psrc(2) := fpPhySrcVec(2) 138 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 139 uops(i).eliminatedMove := isMove(i) 140 141 // update pdest 142 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 143 // normal fp inst 144 Mux(needFpDest(i), fpFreeList.io.allocatePhyReg(i), 145 /* default */0.U)) 146 147 // Assign performance counters 148 uops(i).debugInfo.renameTime := GTimer() 149 150 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 151 io.out(i).bits := uops(i) 152 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 153 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 154 } 155 156 // write speculative rename table 157 // we update rat later inside commit code 158 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 159 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 160 161 intRefCounter.io.allocate(i).valid := intSpecWen(i) 162 intRefCounter.io.allocate(i).bits := io.out(i).bits.pdest 163 } 164 165 /** 166 * How to set psrc: 167 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 168 * - default: psrc from RAT 169 * How to set pdest: 170 * - Mux(isMove, psrc, pdest_from_freelist). 171 * 172 * The critical path of rename lies here: 173 * When move elimination is enabled, we need to update the rat with psrc. 174 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 175 * 176 * If we expand these logic for pdest(N): 177 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 178 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 179 * Mux(bypass(N, N - 2), pdest(N - 2), 180 * ... 181 * Mux(bypass(N, 0), pdest(0), 182 * rat_out(N))...)), 183 * freelist_out(N)) 184 */ 185 // a simple functional model for now 186 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 187 val bypassCond = Wire(Vec(4, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 188 for (i <- 1 until RenameWidth) { 189 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 190 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 191 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 192 for ((((cond1, cond2), t), j) <- fpCond.zip(intCond).zip(target).zipWithIndex) { 193 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 194 val indexMatch = in.bits.ctrl.ldest === t 195 val writeMatch = cond2 && needIntDest(j) || cond1 && needFpDest(j) 196 indexMatch && writeMatch 197 } 198 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 199 } 200 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 201 (z, next) => Mux(next._2, next._1, z) 202 } 203 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 204 (z, next) => Mux(next._2, next._1, z) 205 } 206 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 207 (z, next) => Mux(next._2, next._1, z) 208 } 209 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).old_pdest) { 210 (z, next) => Mux(next._2, next._1, z) 211 } 212 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 213 } 214 215 // calculate lsq space requirement 216 val isLs = VecInit(uops.map(uop => FuType.isLoadStore(uop.ctrl.fuType))) 217 val isStore = VecInit(uops.map(uop => FuType.isStoreExu(uop.ctrl.fuType))) 218 val isAMO = VecInit(uops.map(uop => FuType.isAMO(uop.ctrl.fuType))) 219 io.dispatchInfo.lsqNeedAlloc := VecInit((0 until RenameWidth).map(i => 220 Mux(isLs(i), Mux(isStore(i) && !isAMO(i), 2.U, 1.U), 0.U))) 221 222 /** 223 * Instructions commit: update freelist and rename table 224 */ 225 for (i <- 0 until CommitWidth) { 226 227 Seq((io.intRenamePorts, false), (io.fpRenamePorts, true)) foreach { case (rat, fp) => 228 // is valid commit req and given instruction has destination register 229 val commitDestValid = io.robCommits.valid(i) && needDestRegCommit(fp, io.robCommits.info(i)) 230 XSDebug(p"isFp[${fp}]index[$i]-commitDestValid:$commitDestValid,isWalk:${io.robCommits.isWalk}\n") 231 232 /* 233 I. RAT Update 234 */ 235 236 // walk back write - restore spec state : ldest => old_pdest 237 if (fp && i < RenameWidth) { 238 // When redirect happens (mis-prediction), don't update the rename table 239 rat(i).wen := fpSpecWen(i) 240 rat(i).addr := uops(i).ctrl.ldest 241 rat(i).data := fpFreeList.io.allocatePhyReg(i) 242 } else if (!fp && i < RenameWidth) { 243 rat(i).wen := intSpecWen(i) 244 rat(i).addr := uops(i).ctrl.ldest 245 rat(i).data := io.out(i).bits.pdest 246 } 247 248 /* 249 II. Free List Update 250 */ 251 if (fp) { // Float Point free list 252 fpFreeList.io.freeReq(i) := commitDestValid && !io.robCommits.isWalk 253 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 254 } else { // Integer free list 255 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 256 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 257 } 258 } 259 intRefCounter.io.deallocate(i).valid := io.robCommits.valid(i) && needDestRegCommit(false, io.robCommits.info(i)) 260 intRefCounter.io.deallocate(i).bits := Mux(io.robCommits.isWalk, io.robCommits.info(i).pdest, io.robCommits.info(i).old_pdest) 261 } 262 263 /* 264 Debug and performance counters 265 */ 266 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 267 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 268 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 269 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 270 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 271 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 272 p"old_pdest:${out.bits.old_pdest}\n" 273 ) 274 } 275 276 for((x,y) <- io.in.zip(io.out)){ 277 printRenameInfo(x, y) 278 } 279 280 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 281 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.valid.asUInt)}\n") 282 for (i <- 0 until CommitWidth) { 283 val info = io.robCommits.info(i) 284 XSDebug(io.robCommits.isWalk && io.robCommits.valid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 285 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " + p"eliminatedMove:${info.eliminatedMove} " + 286 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 287 } 288 289 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 290 291 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 292 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 293 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 294 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 295 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 296 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 297 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 298 299 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire() && out.bits.ctrl.isMove))) 300} 301